It's interesting that they're seeing so much support for the F series. The products make sense, but there was no way of knowing if it was niche or not.
I wonder if this will mean they'll have similar parts for the next gen of Threadripper too? Last gen they stopped offering those lower core count TR CPUs and everyone had to buy the big ones whether they wanted to or not.
Is it time to bring back the embedded DRAM (eDRAM) cache rumours?
For those who don't know, IBM developed eDRAM on their 14 nm process so they could put very large L4 caches into their mainframe and Power systems. Then they sold their foundry business to GlobalFoundries. It's not clear if the Epyc IO die uses precisely this process -- if it does, they may well have considered it worthwhile licensing the eDRAM technology. By the time you've done a custom die, manufacturing costs are miniscule.
Incidentally, this does show one of the fascinating aspects of the Epyc architecture -- it must cost a lot less to tape out a 14nm IO chip than something on 7 nm, meaning per-customer IO chips are quite possible.
It's also possible that they've put the Cray interconnects right onto the IO die -- again, once you're doing a custom IO die, why not?
It looks like they need traditional GPUs for the system to get the teraflops they want.
Excellent. Concerning the code names, where is there to go after Genoa? I doubt they want to market Bologna. I'm sure it's a very nice city, but the meat product connotations would be difficult to overcome. In the GPU arena I found the fish themes very amusing.
As an Italian living close by Milan I'm flattered by associatiom with such a powerful product :) Looking for that party in Genoa! Where does it come from the idea of Italian cities as codenames?
NGL I skimmed the article to see where they were going after Milan. I actually expected them to continue north into Switzerland so Geneva Bern Zurich etc, not to swerve southwest to Genoa...
The IO-die power consumption is curious. Norrod claims that AMD has increased its efficiency, while Anandtech testing shows an ~30W increase in power consumption. Are the IO performance improvements really worth the extra power?
Spelling and grammar errors: "That will initially be fairly specialized to be to be candid,..." Excess "to be": "That will initially be fairly specialized to be candid,..."
So Forrest just confirmed that there are SKU's under development with HBM. That sounds expensive, since not only do they need the HBM itself, but also the underlying silicon interposer. I think that would require a redesign of the package, unless they're able to do something like EMIB.
The additional power is going to be difficult to handle, so clocks would have to be lower. If they're redesigning the package with an interposer, it might be an interesting experiment to put the Epyc dies on the interposer, saving the power cost of driving bits over the organic substrate.
With some high-end systems adopting water cooling, maybe at some point they offer the highest performance SKU's with 64GB HBM on 4 stacks, full I/O, and high clock rates, at a 400w peak TDP for water-cooled systems only.
Unfortunately, since he mentioned HBM, not eDRAM, I don't think we'll see an L4 cache on the I/O die.
"You can see a bifurcation coming in the roadmap, where there are parts that have different memory hierarchies. Maybe with storage class memory as the main store with an HBM - on die, or a smaller memory almost like an L4 cache, or maybe a software managed resource that the application can take advantage of. But anyway, I think you’ll see innovation in the memory system in the next few years."
Forrest answered this question, about "PCIe". But somewhere here, they should say that this is on CCIX links. The CCIX supportive PHY will operate in PCIe 4.0 modes, and also support Extended Speed Modes (ESM) for Extended Data Rate (EDR) support. So endpoint devices / accelerators using CCIX, attached to Milan can take advantage of ESM if their PHYs support it. This is not part of PCI Express Base capability. This is a CCIX feature.
> FN: Yes, oh yes, yes, yes. Exactly. Overclocking the PCIe. Overclocking is probably the wrong way to put it! There’s a thing called ESM, Extended Speed Mode, it’s a standard and we support it.
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yelped - Monday, March 15, 2021 - link
Incredible interview!Mr Perfect - Monday, March 15, 2021 - link
It's interesting that they're seeing so much support for the F series. The products make sense, but there was no way of knowing if it was niche or not.I wonder if this will mean they'll have similar parts for the next gen of Threadripper too? Last gen they stopped offering those lower core count TR CPUs and everyone had to buy the big ones whether they wanted to or not.
Slash3 - Tuesday, March 16, 2021 - link
It also pushed a lot of people to compromise and go with a 3950X, or even Intel's 10940X/10980XE instead.outsideloop - Monday, March 15, 2021 - link
Please speculate on Trento, Ian! On-EPYC GPU dies? GPU incorporated into the IO die?Ian Cutress - Monday, March 15, 2021 - link
HBM on package maybejamesindevon - Tuesday, March 16, 2021 - link
Is it time to bring back the embedded DRAM (eDRAM) cache rumours?For those who don't know, IBM developed eDRAM on their 14 nm process so they could put very large L4 caches into their mainframe and Power systems. Then they sold their foundry business to GlobalFoundries. It's not clear if the Epyc IO die uses precisely this process -- if it does, they may well have considered it worthwhile licensing the eDRAM technology. By the time you've done a custom die, manufacturing costs are miniscule.
Incidentally, this does show one of the fascinating aspects of the Epyc architecture -- it must cost a lot less to tape out a 14nm IO chip than something on 7 nm, meaning per-customer IO chips are quite possible.
It's also possible that they've put the Cray interconnects right onto the IO die -- again, once you're doing a custom IO die, why not?
It looks like they need traditional GPUs for the system to get the teraflops they want.
eva02langley - Tuesday, March 16, 2021 - link
I will read it this morning. I just love hearing about Forest, he is such passionate.CrystalCowboy - Tuesday, March 16, 2021 - link
Excellent. Concerning the code names, where is there to go after Genoa? I doubt they want to market Bologna. I'm sure it's a very nice city, but the meat product connotations would be difficult to overcome. In the GPU arena I found the fish themes very amusing.Ian Cutress - Tuesday, March 16, 2021 - link
Some have suggested Turin after Genoa, though AMD hasn't commented.Also: Florence, Bari, Verona, Venice, Messina, Brescia, Parma, Moderna, Ferrara, Monza, Forli, Vicenza, Novara, Ancona, Pesaro, Lecce, Pisa, Lucca, Como, Imola, Massa, Potenza, Savona, Acerra, Trani, Portici, Siena...
neoagentsmith - Wednesday, March 17, 2021 - link
As an Italian living close by Milan I'm flattered by associatiom with such a powerful product :)Looking for that party in Genoa!
Where does it come from the idea of Italian cities as codenames?
Aleph0 - Thursday, March 18, 2021 - link
NGL I skimmed the article to see where they were going after Milan. I actually expected them to continue north into Switzerland so Geneva Bern Zurich etc, not to swerve southwest to Genoa...CrystalCowboy - Tuesday, March 16, 2021 - link
It might be fun to port a few PS5 games to Frontier.Rudde - Tuesday, March 16, 2021 - link
The IO-die power consumption is curious. Norrod claims that AMD has increased its efficiency, while Anandtech testing shows an ~30W increase in power consumption. Are the IO performance improvements really worth the extra power?ballsystemlord - Wednesday, March 17, 2021 - link
Spelling and grammar errors:"That will initially be fairly specialized to be to be candid,..."
Excess "to be":
"That will initially be fairly specialized to be candid,..."
davidefreeman - Saturday, March 20, 2021 - link
So Forrest just confirmed that there are SKU's under development with HBM. That sounds expensive, since not only do they need the HBM itself, but also the underlying silicon interposer. I think that would require a redesign of the package, unless they're able to do something like EMIB.The additional power is going to be difficult to handle, so clocks would have to be lower. If they're redesigning the package with an interposer, it might be an interesting experiment to put the Epyc dies on the interposer, saving the power cost of driving bits over the organic substrate.
With some high-end systems adopting water cooling, maybe at some point they offer the highest performance SKU's with 64GB HBM on 4 stacks, full I/O, and high clock rates, at a 400w peak TDP for water-cooled systems only.
Unfortunately, since he mentioned HBM, not eDRAM, I don't think we'll see an L4 cache on the I/O die.
Makste - Monday, March 22, 2021 - link
"You can see a bifurcation coming in the roadmap, where there are parts that have different memory hierarchies. Maybe with storage class memory as the main store with an HBM - on die, or a smaller memory almost like an L4 cache, or maybe a software managed resource that the application can take advantage of. But anyway, I think you’ll see innovation in the memory system in the next few years."Very interesting lay out of points.
lc0 - Thursday, May 6, 2021 - link
Forrest answered this question, about "PCIe". But somewhere here, they should say that this is on CCIX links. The CCIX supportive PHY will operate in PCIe 4.0 modes, and also support Extended Speed Modes (ESM) for Extended Data Rate (EDR) support. So endpoint devices / accelerators using CCIX, attached to Milan can take advantage of ESM if their PHYs support it.This is not part of PCI Express Base capability. This is a CCIX feature.
> FN: Yes, oh yes, yes, yes. Exactly. Overclocking the PCIe. Overclocking is probably the wrong way to put it! There’s a thing called ESM, Extended Speed Mode, it’s a standard and we support it.
kavontoy - Monday, May 10, 2021 - link
No one charges the Dream ... !!! https://unblocked-gamesez.comRiyasharma - Friday, May 14, 2021 - link
Very interesting interviewhttps://bloggermanyu.com/