What about the proper metric, bits (or transistors) per sq mm (in SRAM)? Those "nm" designations have absolutely nothing to do with reality, pure marketing. And it would be great if everybody would slow down their marketing, because for a long time it is just fraud. Intel's "10 nm" process have been a total failure of course, even if they start mass production on it today and even if it is going to be faster and more energy efficient than "14+++", in terms of time and cost it took.
It would be fantastic if Anandtech could have an investigation into what has happened, conducting some interviews with anonymous sources currently or formerly with Intel. Have they lost real talent? To whom, Samsung? Did they elevate wrong, incompetent people into management? Have they been affected by political considerations, like pushing "diversity" instead of ultimate competence?
From what I read it seems like their 10 nm process was just too ambitous. They get the best density among competing processes, if they're successful, but require 5-6 lithography steps for the critical layers. TSMC and SLI get away with quadruple patterning, which yields a lower density of transistors but increases yield. Better have one bird in the hand than 2 on the roof.
Color me skeptical that SLI is going to launch a notably improved process every 6 months for the next 3 years. Even TSMC is only talking about 1 a year.
And I'll be very surprised if Intel is still on 10nm+ for their front-line designs in 2021.
What counts as “significantly” improved? Rather than sneering at SS, LEARN from them. The reason they (and TSMC) are not floundering like INTC is that they don’t go in for your “significant” improvements; they go in for small tweaks every few months. Then when something fails, it’s not a catastrophe to figure out the problem and correct.
Compare with INTC trying to boost density by 2.7x in one leap by boiling the ocean — and then discovering that they’re going to need a bigger blowtorch than they have available...
I am gonna guess that all of these companies that rushed down the nano meter scale so fast the last few years are wishing they would have slowed down years ago and just worked out the problem og the bigger nm nodes back then so they would not be in a pickle like they will be in the near future when they have no where left to go except invent something totally new to work with.
No one "rushed down the scale" in any way. Each of those nodes generally has a major process change to either transistor design or interconnect scheme, justifying the 'node' shrink based on performance gains. LSI definitely likes to market a minor change as bigger than such, more than the others probably. However, the current issues with these technologies didn't EXIST at higher nodes (except Intel's problems with 10nm, they scaled geometry too aggressively without changing fundamental design, hence hexa-patterning), so they aren't unsolved problems everyone just lives with while forging ahead.
I refuse to be excited until companies start announcing negative numeric values for their manufacturing processes. For instance, I would like to see -5nm since that means using my phone will charge instead of discharge my battery and absorb rather than create heat, dumping it into some dark, ethereal realm that exists outside of the observable Universe. Then I can stick my phone in my crotch to cool it off in the summer and minimize unsightly sweat generation in my nether regions. That translates into milking another day or two out of my undergarments and saves me from doing as much laundry. Mom would be so proud of me!
There are always smaller measurements. 0nm would be 100um. The problem is the Silicon atom is only 0.2nm wide so when you get to 1nm you are constructing wires that are only 5 atoms wide. Quantum effects at this size are likely to become so bad they simply can't go smaller.
I remember an article from several years ago that talked about 5nm probably being the point where quantum effects may make shrinking things any more impossible. This should be obvious as even at 14nm and smaller they are having to dope the traces with all kinds of stuff (FinFET etc) to negate the quantum effects.
If you have a quantum effect problem below 3-5 nm, you switch to tunnel field effect transistors (TFETs) which actually use the effect to operate. Voila, problem solved.
I thought Extreme UV (EUV) only worked till 7nm and after that they had to go to X-Ray lithography and none of the tools are even close to being ready.
I thought that's why Intel had slowed down was because they didn't want to get stuck on 7nm for a decade waiting for the X-ray lithography tools to finally become available so they worked on stretching out the existing process tech while the tools people worked to make X-ray lithography viable.
They expect to write 5 nm class processes with EUV and higher numerical apertures. It's not easy, as always with EUV, but probably not a show stopper. Afterwards they'll probably need multi patterning with EUV (as with the current 193 nm tools).
High NA is definitely the path forward with EUV, same as it was with KrF lasers. There are some obvious challenges in scaling EUV re: optics, but it should also be noted that critical dimensions like gate half-pitch at "5nm" are still on the order of ~15-20nm. The longterm future of semicon will involve a LOT of new materials science and novel transistor designs, but silicon probably has legs through what most companies will call 2/3nm nodes.
DUV (Deep Ultra Violet) will continue to be used down to 7nm (TSMC, Samsung, GF) or 10nm (Intel), and EUV will be introduced at 7nm (2nd generation TSMC, SS, GF; 1st generation Intel) subsequently. EUV will be used at least until 3nm nodes (whatever 3nm really means when you start stacking the gates vertically with GAA).
Samsung has some catching up to do. I doubt anything much has changed in the past two years or so. Back then, Apple split its SoC production between Samsung and TSMC, as we all know. It turned out that TSMCs 16nm was 20% more efficient than Samsung’s 14nm. I doubt that ratio has changed much since then with newer process steps.
I also read with amusement about 3nm. I’ll believe it when I see it.
Pellicles are planned, but that bit has been lagging behind other aspects of mask design for EUV. Attenuation is still unacceptably high (>25% last I saw, with a goal <10%). Effectively those doing early EUV insertion have a dedicated scanner for CT or M1 or whatever, so the reticle basically doesn't go anywhere, limited inspections, low risk.
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25 Comments
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shabby - Thursday, May 24, 2018 - link
Slow down samsung, intel is still stuck in double digit nm.peevee - Thursday, May 24, 2018 - link
What about the proper metric, bits (or transistors) per sq mm (in SRAM)? Those "nm" designations have absolutely nothing to do with reality, pure marketing. And it would be great if everybody would slow down their marketing, because for a long time it is just fraud.Intel's "10 nm" process have been a total failure of course, even if they start mass production on it today and even if it is going to be faster and more energy efficient than "14+++", in terms of time and cost it took.
It would be fantastic if Anandtech could have an investigation into what has happened, conducting some interviews with anonymous sources currently or formerly with Intel. Have they lost real talent? To whom, Samsung? Did they elevate wrong, incompetent people into management? Have they been affected by political considerations, like pushing "diversity" instead of ultimate competence?
p1esk - Thursday, May 24, 2018 - link
I like the idea of such interviews. That would be real journalism in action.MrSpadge - Thursday, May 24, 2018 - link
From what I read it seems like their 10 nm process was just too ambitous. They get the best density among competing processes, if they're successful, but require 5-6 lithography steps for the critical layers. TSMC and SLI get away with quadruple patterning, which yields a lower density of transistors but increases yield. Better have one bird in the hand than 2 on the roof.jwcalla - Thursday, May 24, 2018 - link
inb4 somebody mentions that Samsung 3nm is still larger than Intel 32nm... since we hear that story on every one of these articles.A5 - Thursday, May 24, 2018 - link
Color me skeptical that SLI is going to launch a notably improved process every 6 months for the next 3 years. Even TSMC is only talking about 1 a year.And I'll be very surprised if Intel is still on 10nm+ for their front-line designs in 2021.
name99 - Friday, May 25, 2018 - link
What counts as “significantly” improved? Rather than sneering at SS, LEARN from them.The reason they (and TSMC) are not floundering like INTC is that they don’t go in for your “significant” improvements; they go in for small tweaks every few months. Then when something fails, it’s not a catastrophe to figure out the problem and correct.
Compare with INTC trying to boost density by 2.7x in one leap by boiling the ocean — and then discovering that they’re going to need a bigger blowtorch than they have available...
rocky12345 - Thursday, May 24, 2018 - link
I am gonna guess that all of these companies that rushed down the nano meter scale so fast the last few years are wishing they would have slowed down years ago and just worked out the problem og the bigger nm nodes back then so they would not be in a pickle like they will be in the near future when they have no where left to go except invent something totally new to work with.FullmetalTitan - Friday, May 25, 2018 - link
No one "rushed down the scale" in any way. Each of those nodes generally has a major process change to either transistor design or interconnect scheme, justifying the 'node' shrink based on performance gains. LSI definitely likes to market a minor change as bigger than such, more than the others probably. However, the current issues with these technologies didn't EXIST at higher nodes (except Intel's problems with 10nm, they scaled geometry too aggressively without changing fundamental design, hence hexa-patterning), so they aren't unsolved problems everyone just lives with while forging ahead.attila123 - Sunday, January 19, 2020 - link
Well in 2019 they went to 3nm. Which most people thought was impossible.PeachNCream - Thursday, May 24, 2018 - link
I refuse to be excited until companies start announcing negative numeric values for their manufacturing processes. For instance, I would like to see -5nm since that means using my phone will charge instead of discharge my battery and absorb rather than create heat, dumping it into some dark, ethereal realm that exists outside of the observable Universe. Then I can stick my phone in my crotch to cool it off in the summer and minimize unsightly sweat generation in my nether regions. That translates into milking another day or two out of my undergarments and saves me from doing as much laundry. Mom would be so proud of me!bug77 - Friday, May 25, 2018 - link
Why stop there?Instead of negative, you should demand complex numbers. Those would be fun to have.
TheWereCat - Sunday, May 27, 2018 - link
So you will have to be carrying discharger with you everywhere to not overcharge and explode your batteries?PeachNCream - Tuesday, May 29, 2018 - link
Nope! I'm okay with overcharging my phone's battery to the point that it bursts while in my pants.kf27fix - Thursday, May 24, 2018 - link
3 more nm and we will be down to 0 nm. Then, things will start to look interesting...rahvin - Thursday, May 24, 2018 - link
There are always smaller measurements. 0nm would be 100um. The problem is the Silicon atom is only 0.2nm wide so when you get to 1nm you are constructing wires that are only 5 atoms wide. Quantum effects at this size are likely to become so bad they simply can't go smaller.I remember an article from several years ago that talked about 5nm probably being the point where quantum effects may make shrinking things any more impossible. This should be obvious as even at 14nm and smaller they are having to dope the traces with all kinds of stuff (FinFET etc) to negate the quantum effects.
nandnandnand - Friday, May 25, 2018 - link
If you have a quantum effect problem below 3-5 nm, you switch to tunnel field effect transistors (TFETs) which actually use the effect to operate. Voila, problem solved.https://en.wikipedia.org/wiki/Tunnel_field-effect_...
rahvin - Thursday, May 24, 2018 - link
I thought Extreme UV (EUV) only worked till 7nm and after that they had to go to X-Ray lithography and none of the tools are even close to being ready.I thought that's why Intel had slowed down was because they didn't want to get stuck on 7nm for a decade waiting for the X-ray lithography tools to finally become available so they worked on stretching out the existing process tech while the tools people worked to make X-ray lithography viable.
MrSpadge - Thursday, May 24, 2018 - link
They expect to write 5 nm class processes with EUV and higher numerical apertures. It's not easy, as always with EUV, but probably not a show stopper. Afterwards they'll probably need multi patterning with EUV (as with the current 193 nm tools).FullmetalTitan - Friday, May 25, 2018 - link
High NA is definitely the path forward with EUV, same as it was with KrF lasers. There are some obvious challenges in scaling EUV re: optics, but it should also be noted that critical dimensions like gate half-pitch at "5nm" are still on the order of ~15-20nm. The longterm future of semicon will involve a LOT of new materials science and novel transistor designs, but silicon probably has legs through what most companies will call 2/3nm nodes.psychobriggsy - Monday, June 4, 2018 - link
DUV (Deep Ultra Violet) will continue to be used down to 7nm (TSMC, Samsung, GF) or 10nm (Intel), and EUV will be introduced at 7nm (2nd generation TSMC, SS, GF; 1st generation Intel) subsequently. EUV will be used at least until 3nm nodes (whatever 3nm really means when you start stacking the gates vertically with GAA).Anymoore - Sunday, May 27, 2018 - link
7LPP will not migrate to 5LPE , that's why they need to do an independent 5LPE development after stopping 7LPP development.melgross - Monday, May 28, 2018 - link
Samsung has some catching up to do. I doubt anything much has changed in the past two years or so. Back then, Apple split its SoC production between Samsung and TSMC, as we all know. It turned out that TSMCs 16nm was 20% more efficient than Samsung’s 14nm. I doubt that ratio has changed much since then with newer process steps.I also read with amusement about 3nm. I’ll believe it when I see it.
Anymoore - Thursday, June 28, 2018 - link
Samsung 7nm EUV will not use pellicles, even with metal layers. That should even scare Qualcomm off.FullmetalTitan - Thursday, August 2, 2018 - link
Update: It didn't.Pellicles are planned, but that bit has been lagging behind other aspects of mask design for EUV. Attenuation is still unacceptably high (>25% last I saw, with a goal <10%). Effectively those doing early EUV insertion have a dedicated scanner for CT or M1 or whatever, so the reticle basically doesn't go anywhere, limited inspections, low risk.