Given the timing of yesterday's Cortex A53 based Snapdragon 410 announcement, our latest Ask the Experts installment couldn't be better. Peter Greenhalgh, lead architect of the Cortex A53, has agreed to spend some time with us and answer any burning questions you might have on your mind about ARM, directly.

Peter has worked in ARM's processor division for 13 years and worked on the Cortex R4, Cortex A8 and Cortex A5 (as well as the ARM1176JZF-S and ARM1136JF-S). He was lead architect of the Cortex A7 and ARM's big.LITTLE technology as well. 

Later this month I'll be doing a live discussion with Peter via Google Hangouts, but you guys get first crack at him. If you have any questions about Cortex A7, Cortex A53, big.LITTLE or pretty much anything else ARM related fire away in the comments below. Peter will be answering your questions personally in the next week.

Please help make Peter feel at home here on AnandTech by impressing him with your questions. Do a good job here and I might be able to even convince him to give away some ARM powered goodies...

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  • MrSpadge - Tuesday, December 10, 2013 - link

    Interesting: you apparently completely misunderstood his question, yet "I assume Mediatek will make another 8-core one with Cortex A53" is what I would answer as well. 8 smaller cores are cheaper than 2*4 in big.LITTLE and does sound impressive to the uniformed. Reply
  • lukarak - Tuesday, December 10, 2013 - link

    Exactly, I was wondering that while today it is cheaper/easier to make 8x A7 than say 2x A15 2xA7 big.LITTLE, will that be the case with A53 and A57? Reply
  • Wilco1 - Tuesday, December 10, 2013 - link

    Big cores are larger than small cores (surprise!), so the SoC will be more expensive to produce if it has big cores rather than only little cores. But then again it will be faster too. Reply
  • lukarak - Wednesday, December 11, 2013 - link

    Yes, but I'm talking about an 8 core A7 vs 4 core A15/A7 combo, as in 2 A15 cores and 2 A7 cores in big.LITTLE. So it's not the same number of cores. Reply
  • Wilco1 - Thursday, December 12, 2013 - link

    Excluding L2, A15 is about 4 times as large as A7 (http://chip-architect.com/news/2013_core_sizes_768... So 2xA15 + 2xA7 is about the size of 10xA7, ie. larger than 8xA7. A15 will also need a larger L2 than A7 due to its higher performance. Reply
  • Peter Greenhalgh - Wednesday, December 11, 2013 - link

    Hi Lukarak,

    We expect to see a range of platform configurations using Cortex-A53. A 4+4 Cortex-A53 platform configuration is fully supported and a logical progression from a 4+4 Cortex-A7 platform. A Cortex-A57 in the volume smartphone markets is less likely, but that’s a decision in the hands of the ARM partners. It will be interesting to see the range of Cortex-A53 platforms and configurations announced by partners over the coming months.
    Reply
  • ehsan.nitol - Tuesday, December 10, 2013 - link

    Hi there, I have some questions.

    We have already seen how well Qualcomm's Cortex A7 can perform thanks to Moto G. How much will it improve with the new Cortex A53? What will be the core and performance wise difference? How will you compare it against Cortex A9, A12 and A15 in terms of performance, battery consumption and all.

    With the Exynos Octa core processor Battery Test we haven't seen much battery improvements compared to Qualcomm's Snapdragon 600 and 800 Processor. How will it perform this time?

    What is ARM planning do with its Mali GPU? What will be next after Cortex A53 and A57?
    Reply
  • deputc26 - Tuesday, December 10, 2013 - link

    This what will the IPC improve,nets be from A7 to A53 Reply
  • deputc26 - Tuesday, December 10, 2013 - link

    Typing on an iPad, I blame Tim Cook for the errors above. Reply
  • Peter Greenhalgh - Wednesday, December 11, 2013 - link

    Hi Ehsan,

    Cortex-A53 has the same pipeline length as Cortex-A7 so I would expect to see similar frequencies when implemented on the same process geometry. Within the same pipeline length the design team focussed on increasing dual-issue, in-order performance as far as we possibly could. This involved symmetric dual-issue of most of the instruction set, more forwarding paths in the datapaths, reduced issue latency, larger & more associative TLB, vastly increased conditional and indirect branch prediction resources and expanded instruction and data prefetching. The result of all these changes is an increase in SPECInt-2000 performance from 0.35-SPEC/Mhz on Cortex-A7 to 0.50-SPEC/Mhz on Cortex-A53. This should provide a noticeable performance uplift on the next generation of smartphones using Cortex-A53.
    Reply

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