Samsung has begun mass production of the industry’s first 16 GB LPDDR5 memory for upcoming smartphones, such as the Galaxy S20 Ultra 5G handsets. The new DRAM devices not only offer higher capacity, but they are also 30% faster than previous-generation LPDDR4X-4266 used for previous-generation cellphones.

Samsung’s latest 16 GB LPDDR5 package consists of eight 12 Gb chips and four 8 Gb chips featuring a 5500 MT/s data transfer rate that can provide bandwidth of up to 44 GB/s. The very complex 12-device assembly is called a ‘mixed mode package’ because it contains DRAM devices that are accessed differently in different ranks. Samsung does not publish voltages of the new multi-chip 16 GB DRAM assembly, but only claims that it delivers more than 20% energy savings when compared to an 8 GB LPDDR4X package. Meanwhile, we do know that LPDDR5 memory chips feature a variable voltage that is up to 1.1 V.

The 12 Gb LPDDR5 devices are made using Samsung’s 2nd Generation 10 nm-class fabrication technology (also known as 1y nm), but the company does not disclose which manufacturing process is used to build 8 Gb LPDDR5 devices (though we are probably talking about 1y nm here as well).

Typically, DRAM makers make mass production announcements after they ship the first batch of products to a client. Considering that Samsung’s Galaxy S20 Ultra features 16 GB of LPDDR5 memory, it is more than reasonable to assume that it uses the company’s latest 16 GB LPDDR5-5500 DRAM package.

In the second half of this year Samsung plans to start production of 16 Gb LPDDR5 devices using its 3rd Generation 10 nm-class fabrication process (aka 1z). These chips will support speeds up to 6400 MT/s, but to take advantage of them Samsung will have to develop an SoC that supports such a high data transfer rate. Meanwhile, capacities of these upcoming LPDDR5 assembles remain to be seen.

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Source: Samsung

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  • azfacea - Wednesday, February 26, 2020 - link

    Smartphones stack the DRAM on top of the SOC, so signaling doesn't go across the PCB, which neutralizes some of the advantage of HBM.

    well if thata the case then i dont seem to know whats going on lol.
    but joking aside, i dont think its like u describe either. they dont use interposers or 3d stacking yet. and many phones do put it across the PCB.
    Reply
  • azfacea - Wednesday, February 26, 2020 - link

    just to add: it looks like LPDDR5 is a form of "package on package" and it will use way more power per bit than HBM/2.5D/3D stacking/ or other ways of connecting TSVs together directly.

    so it looks i did know what was going on.
    Reply
  • levizx - Wednesday, February 26, 2020 - link

    Name that "many phones"? I know for certain Snapdragon 6/7/8 series come with packaged LPDDR for years, same with Kirin and Apple A. Reply
  • Diogene7 - Wednesday, February 26, 2020 - link

    @azfacea : Well I wish as well to see smartphones with Non Volatile Memory (NVM) High Bandwith Memory (HBM) DRAM with at least 64GB of NVM HBM made for example of MRAM (SOT-MRAM), or Nantero Carbon Nanotubes RAM (NRAM).

    It would make a pool of low latency memory with the full Operating System (OS) in it, and would greatly improve the user experience like replacing an HDD by a SSD make feel a laptop computer much more snappy.

    Unfortunately, such dream is unlikely to happen before at least 2025 as DRAM manufacturers and smartphone manufacturers don’t yet have much incentive to invest in such disrupting technologies (too costly, and therefore not profitable enough)
    Reply
  • Santoval - Wednesday, February 26, 2020 - link

    "HBM is vastly more efficient than LPDDR5 in terms energy per bit."
    I strongly doubt that's the case. I think you are confusing LPDDR4/5 with DDR4/5 and GDDR5/6. Even against those though HBM is nowhere close to being "vastly" more energy efficient. For HBM to be so much more efficient than LPDDR5 or even more efficient at all, an LP version of HBM would need to be developed.
    That has not yet happened, and as far as I know there are no plans for that to happen. Merely downclocking HBM would not be a solution. If it was LPDDR would not exist, only downclocked DDR.
    Reply
  • peevee - Tuesday, February 25, 2020 - link

    Put those on SODIMMs, plug 4 of those into 4 sides of a next-gen desktop CPU with 4 memory channels for low latency and simple MB, and I will buy. Reply
  • azfacea - Tuesday, February 25, 2020 - link

    i think its time for quad channel memory in desktop. memory bandwidth gains have been pretty poor compared to CPU core count and APU growth. just going to ddr5 is not going to do it. we need quad channel ddr5.
    also putting 2 dimms on a single channel can never be a good thing for latency and latency sensitive gaming.

    there is a small chance AMD will grant my wish with AM5, there is 0.00 % chance with shintel
    Reply
  • bug77 - Wednesday, February 26, 2020 - link

    You have quad-channel memory on desktop, you just need to buy a Threadripper or a Core XE. Reply
  • peevee - Thursday, February 27, 2020 - link

    4-channel memory on desktop is most useful for CPUs with embedded graphics, neither TR no Core XE have that, and too expensive to have that anyway.
    4 channels of DDR5 are fast enough to have embedded graphics of the performance similar to Radeon 5500 or Geforce 1650. And in homogeneous configuration would enable extensibility of iGPU by add-in GPU instead of replacing it completely.
    Reply
  • ZoZo - Wednesday, February 26, 2020 - link

    Hum... by which logic can an increase in the number of memory channels translate in better latency? In fact, in practice, that's the opposite of what we see on HEDT platforms. They have significantly worse memory latency than the mainstream ones. Reply

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