RISC-V

Hot Chips has gone virtual this year! Lots of talks on lots of products, including Tiger Lake, Xe, POWER10, Xbox Series X, TPUv3, and a special Raja Koduri Keynote. Stay tuned at AnandTech for our live blogs as we commentate on each talk.

Hot Chips 2020 Live Blog: Alibaba Xuantie-910 RISC-V CPU (3:00pm PT)

Hot Chips has gone virtual this year! Lots of talks on lots of products, including Tiger Lake, Xe, POWER10, Xbox Series X, TPUv3, and a special Raja Koduri Keynote...

6 by Dr. Ian Cutress on 8/17/2020

Western Digital Rolls-Out Two New SweRV RISC-V Cores For Microcontrollers

Western Digital has added two new processor cores — the SweRV Core EH2 and the SweRV Core EL2 — into its SweRV portfolio of microcontroller CPUs. And, keeping in...

12 by Anton Shilov on 12/13/2019

Samsung to Use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications

At the annual RISC-V Summit this week, Samsung disclosed the use SiFive’s RISC-V cores for upcoming chips for a variety of applications. The company is joining a growing list...

18 by Anton Shilov on 12/12/2019

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable...

13 by Anton Shilov on 11/5/2019

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP

In the last few year’s we’ve seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we’ve seen...

69 by Andrei Frumusanu on 10/30/2019

SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs

SiFive, one of the world’s leading developers of controllers and SoCs based on the RISC-V instruction set, has acquired USB IP portfolio from Innovative Logic, a silicon IP designer...

7 by Anton Shilov on 5/23/2019

Western Digital’s RISC-V "SweRV" Core Design Released For Free

Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as...

14 by Anton Shilov on 2/15/2019

Western Digital Reveals SweRV RISC-V Core, Cache Coherency over Ethernet Initiative

Western Digital this week made three important announcements concerning its RISC-V-based processor initiative launched last year. The company introduced its own SweRV general-purpose core, its OmniXtend cache coherency over...

11 by Anton Shilov on 12/5/2018

Apacer Launches 32-Bit SODIMM for Arm & RISC-V Systems

Apacer has announced a lineup of 32-bit SO-DIMMs designed for systems based on processors featuring Arm, RISC, or RISC-V architectures. The memory modules will enable SoC developers to take...

5 by Anton Shilov on 11/26/2018

Western Digital to Use RISC-V for Controllers, Processors, Purpose-Built Platforms

Western Digital recently announced plans to use the RISC-V ISA across its existing product stack as well as for future products that will combine processing and storage. The company...

10 by Anton Shilov on 12/14/2017

SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips

SiFive, a company established by researchers who invented the RISC-V instruction set architecture in the University of California Berkeley several years ago, has this week announced two platforms which...

10 by Anton Shilov on 7/18/2016

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