I think Intel should have made regular Pentium 4's Prescott with 1MB L2 and 1066MHz bus, Pentium 4 EE should have been Prescott 2MB L2 and 1066MHz bus. There is a bigger difference between the EE and non EE then. 33% bus speed difference would do even less than current EE's advantages, although the newer EE's should have closer clock speed to the regular P4 chips.
Thanks Bozo Galora for your appreciation. I usually don't get that.
KristopherKubicki: I am not sure if calling it internal bus is right. Indeed you need CPU to support the bus, but you need chipset support too. FSB description is here: http://en.wikipedia.org/wiki/Front_side_bus
I'll just say now I might be wrong but wasn't 266 based, way back when, on a 33.3 bus which lends itself to 66.6, to 266.4, and thus to 1065.6? I probably just have not had enough coffee yet, but we dropped the fractions long ago, but it's from that I calculated the cpu speeds.
IntelUser2000: Thanks for the post; i will look into it more. All of the processors your mentioned were P6 based which made sense to me.
I have to look more into the P4-M line, i did not know it had EIST and that was not really documented in anything ive seen yet. I also have not seen anything that says EIST is on Nocona; although its a good idea it should be on all their processors.
I appreciate the info though I have sent some emails to Intel people about it.
"In fact, the most interesting addition we noted with these new processors is the addition of Enhanced Speed Step Technology (EIST, also known as ESS depending on your circles). Up until now, EIST has been limited only to Pentium M processors. For those not familiar with EIST, it is simply a feature which allows a user to dynamically clock the processor during operation; very much like AMD's Cool 'n Quiet."
There is several versions of Enhanced Speed Step Technology.
The first Speed Step capable chip was Pentium III Mobile(Coppermine Mobile), clocking permanently down when in battery power, eg, 1GHz runs at 700MHz on battery power.
The second Speed Step(called Enhanced Speed Step) was featured on Pentium III-M(Tualatin Mobile), while was able to change between two speeds depending on load, eg, 1.2GHz at high demand or 800MHz low demand.
The Pentium 4-M's(not the desktop chip with the speedstep, P4-M is the desktop chip with lower TDP AND SpeedStep) used Pentium III-m's Enhanced SpeedStep technology.
The Third generation of SpeedStep is used on Pentium M, used in Centrino bundle laptops. It has 6 speed grades to switch to depending on demand. But there is more.
"A simple, yet effective method that was pursued in order to reduce power was to identify idle logic and shut it off. This was done locally and globally."
The Pentium 4's with Enhanced Speed Step Technology will use technology from Nocona core Xeon.
"Enhanced Intel Speedstep Technology allows the system to dynamically adjust processor voltage and core frequency, which results in decreased power consumption, which results in decreased heat production, which in turn allows improved acoustics because fans do not need to spin as quickly."
See? The Xeon 90nm and Prescott's EIST just changes clock speed, while Pentium M turns off logic too, plus unlike traditional processors that goes idle when necessary, Pentium M is always idle and goes active when necessary.
P4EEs do price drop, but people usually just discontinue them. I think there were only like 55K P4EE 3.4s made, or some ridiculously low number like that.
I thought the math worked out to 3.46 and 3.73 being 3.25 and 3.5 times 1066.64 of the bus. And most other places are assuming the 3.46 is going to be a 2mb cache chip - did you mistype or do you differ pointedly from that rumormill?
I'm a bit confused. The 6 series processors are suppose to have 2MB L2 cache, correct? They're listed with a 1MB cache on the table. But regardless, without a 1066FSB, they're not very interesting CPUs...
And the first two lines... The Pentium 4 XE 3.73Ghz is listed twice, with two different clock speeds and two different caches. Hmm.
Basically, the only difference between the 6xx series P4 chips and the upcoming P4PXE chips will be the 1066 FSB on the P4PXE - is that right? Then again, cost of the high-end P4P 670 is right up there is the P4PXE, isn't it? Reminds me of the 3800+ and the FX-53....
Do the prices on P4PXE chips ever drop (officially), or are they simply discontinues a la the FX chips? With them being "direct competitors", I'm assuming they're just discontinued (and sold as Xeons).
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17 Comments
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skiboysteve - Sunday, September 12, 2004 - link
you can even go a step further...pentium4 bus actually quad pumps data transmition so its effectivly 1066mhz (or 800 or 533 or 400) for data,
but it only double pumps address transmission, so its effectivly 533mhz (or 400 or 266 or 200) for addresses...
this stuff is all in anandtech articles from when the p4 launched.
skiboysteve - Sunday, September 12, 2004 - link
no need to worry about the p4EE, no one buys them anyway.and its a 266 internal bus x4 = 1066FSB
and you multiply the internal bus to get cpu speed.
this is like, kiddy stuff people.
IntelUser2000 - Monday, September 6, 2004 - link
I think Intel should have made regular Pentium 4's Prescott with 1MB L2 and 1066MHz bus, Pentium 4 EE should have been Prescott 2MB L2 and 1066MHz bus. There is a bigger difference between the EE and non EE then. 33% bus speed difference would do even less than current EE's advantages, although the newer EE's should have closer clock speed to the regular P4 chips.Thanks Bozo Galora for your appreciation. I usually don't get that.
KristopherKubicki: I am not sure if calling it internal bus is right. Indeed you need CPU to support the bus, but you need chipset support too. FSB description is here: http://en.wikipedia.org/wiki/Front_side_bus
Bozo Galora - Friday, September 3, 2004 - link
great post by inteluserKristopherKubicki - Thursday, September 2, 2004 - link
266 INTERNAL bus!! not front side!!Kristopher
Carfax - Thursday, September 2, 2004 - link
So for the capability to run 266FSB, they are going to charge how many hundreds of dollars more?Thats ridiculous in my opinion. Why don't they just add more cache to the P4EE (like 4MB) and make 1066FSB the standard?
Getting a 3.2E with 2MB of L2 cache and overclocking the shit out of it would be a good deal I think..
KristopherKubicki - Thursday, September 2, 2004 - link
Anemone: The multiplier is based off the internal bus. But then it gets quad pumped.Kristopher
Anemone - Thursday, September 2, 2004 - link
I'll just say now I might be wrong but wasn't 266 based, way back when, on a 33.3 bus which lends itself to 66.6, to 266.4, and thus to 1065.6? I probably just have not had enough coffee yet, but we dropped the fractions long ago, but it's from that I calculated the cpu speeds.IntelUser2000 - Thursday, September 2, 2004 - link
You are very welcome :). The link for EIST in Nocona is here: http://www.intel.com/business/bss/products/server/...The info is at the near end of the page. It's called Demand Based Switching.
Cool 'n' Quiet is much similar to Second Generation SpeedStep and PowerNow! Technology. PowerNow has like 20 steps though.
No you do not need to find P4-M info to find it has EIST, here's the link: http://support.intel.com/support/processors/mobile...
KristopherKubicki - Thursday, September 2, 2004 - link
IntelUser2000: Thanks for the post; i will look into it more. All of the processors your mentioned were P6 based which made sense to me.I have to look more into the P4-M line, i did not know it had EIST and that was not really documented in anything ive seen yet. I also have not seen anything that says EIST is on Nocona; although its a good idea it should be on all their processors.
I appreciate the info though I have sent some emails to Intel people about it.
Kristopher
IntelUser2000 - Thursday, September 2, 2004 - link
"In fact, the most interesting addition we noted with these new processors is the addition of Enhanced Speed Step Technology (EIST, also known as ESS depending on your circles). Up until now, EIST has been limited only to Pentium M processors. For those not familiar with EIST, it is simply a feature which allows a user to dynamically clock the processor during operation; very much like AMD's Cool 'n Quiet."There is several versions of Enhanced Speed Step Technology.
The first Speed Step capable chip was Pentium III Mobile(Coppermine Mobile), clocking permanently down when in battery power, eg, 1GHz runs at 700MHz on battery power.
The second Speed Step(called Enhanced Speed Step) was featured on Pentium III-M(Tualatin Mobile), while was able to change between two speeds depending on load, eg, 1.2GHz at high demand or 800MHz low demand.
The Pentium 4-M's(not the desktop chip with the speedstep, P4-M is the desktop chip with lower TDP AND SpeedStep) used Pentium III-m's Enhanced SpeedStep technology.
The Third generation of SpeedStep is used on Pentium M, used in Centrino bundle laptops. It has 6 speed grades to switch to depending on demand. But there is more.
Link: http://www.intel.com/technology/itj/2003/volume07i...
"A simple, yet effective method that was pursued in order to reduce power was to identify idle logic and shut it off. This was done locally and globally."
The Pentium 4's with Enhanced Speed Step Technology will use technology from Nocona core Xeon.
"Enhanced Intel Speedstep Technology allows the system to dynamically adjust processor voltage and core frequency, which results in decreased power consumption, which results in decreased heat production, which in turn allows improved acoustics because fans do not need to spin as quickly."
See? The Xeon 90nm and Prescott's EIST just changes clock speed, while Pentium M turns off logic too, plus unlike traditional processors that goes idle when necessary, Pentium M is always idle and goes active when necessary.
KristopherKubicki - Thursday, September 2, 2004 - link
Anemone: The bus is quadpumped, so its really 266 * 14 and 266 * 13.Kristopher
KristopherKubicki - Thursday, September 2, 2004 - link
Typo on the table but that is all fixed.The 3.46 is 2MB L3 cache, not L2.
P4EEs do price drop, but people usually just discontinue them. I think there were only like 55K P4EE 3.4s made, or some ridiculously low number like that.
Kristopher
IntelUser2000 - Thursday, September 2, 2004 - link
3.46XE is based on 0.13 micron Gallatin core with 2MB L3 cache.3.73XE is based on Prescott with 0.09 micron and 2MB L2 cache.
They are both 1066MHz bus.
Anemone - Thursday, September 2, 2004 - link
I thought the math worked out to 3.46 and 3.73 being 3.25 and 3.5 times 1066.64 of the bus. And most other places are assuming the 3.46 is going to be a 2mb cache chip - did you mistype or do you differ pointedly from that rumormill?Thank you :)
slay9 - Wednesday, September 1, 2004 - link
I'm a bit confused. The 6 series processors are suppose to have 2MB L2 cache, correct? They're listed with a 1MB cache on the table. But regardless, without a 1066FSB, they're not very interesting CPUs...And the first two lines... The Pentium 4 XE 3.73Ghz is listed twice, with two different clock speeds and two different caches. Hmm.
JarredWalton - Wednesday, September 1, 2004 - link
Basically, the only difference between the 6xx series P4 chips and the upcoming P4PXE chips will be the 1066 FSB on the P4PXE - is that right? Then again, cost of the high-end P4P 670 is right up there is the P4PXE, isn't it? Reminds me of the 3800+ and the FX-53....Do the prices on P4PXE chips ever drop (officially), or are they simply discontinues a la the FX chips? With them being "direct competitors", I'm assuming they're just discontinued (and sold as Xeons).