The Skylake CPU Architecture

As with any new Intel architecture, the devil is in the details. Previously at AnandTech we have been able to provide deep dives into what exactly is going on in the belly of the beast, although the launch of Skylake has posed a fair share of problems.

Nominally we rely on a certain amount of openness from the processor/SoC manufacturer in providing low level details that we can verify and/or explain. In the past, this information has typically been provided in advance of the launch by way of several meetings/consultations with discussions talking to the engineers. There are some things we can probe, but others are like a black box. The black box nature of some elements, such as Qualcomm’s Adreno graphics, means that it will remain a mystery until Pandora’s box is opened.

In the lead up to the launch of Intel’s Skylake platform, architecture details have been both thin on the ground and thin in the air, even when it comes down to fundamental details about the EU counts of the integrated graphics, or explanations regarding the change in processor naming scheme. In almost all circumstances, we’ve been told to wait until Intel’s Developer Forum in mid-August for the main reason that the launch today is not the full stack Skylake launch, which will take place later in the quarter. Both Ryan and I will be at IDF taking fastidious notes and asking questions for everyone, but at this point in time a good portion of our analysis comes from information provided by sources other than Intel, and while we trust it, we can't fully verify it as we normally would.

As a result, the details on the following few pages have been formed through investigation, discussion and collaboration outside the normal channels, and may be updated as more information is discovered or confirmed. Some of this information is mirrored in our other coverage in order to offer a complete picture in each article as well. After IDF we plan to put together a more detailed architecture piece as a fundamental block in analyzing our end results.

The CPU

As bad as it sounds, the best image of the underlying processor architecture is the block diagram:

From a CPU connectivity standpoint, we discussed the DDR3L/DDR4 dual memory controller design on the previous page so we won’t go over it again here. On the PCI-Express Graphics allocation side, the Skylake processors will have sixteen PCIe 3.0 lanes to use for directly attached devices to the processor, similar to Intel's previous generation processors. These can be split into a single PCIe 3.0 x16, x8/x8 or x8/x4/x4 with basic motherboard design. (Note that this is different to early reports of Skylake having 20 PCIe 3.0 lanes for GPUs. It does not.)

With this, SLI will work up to x8/x8. If a motherboard supports x8/x4/x4 and a PCIe card is placed into that bottom slot, SLI will not work because only one GPU will have eight lanes. NVIDIA requires a minimum of PCIe x8 in order to enable SLI. Crossfire has no such limitation, which makes the possible configurations interesting. Below we discuss that the chipset has 20 (!) PCIe 3.0 lanes to use in five sets of four lanes, and these could be used for graphics cards as well. That means a motherboard can support x8/x8 from the CPU and PCIe 3.0 x4 from the chipset and end up with either dual-SLI or tri-CFX enabled when all the slots are populated.

DMI 3.0

The processor is connected to the chipset by the four-lane DMI 3.0 interface. The DMI 3.0 protocol is an upgrade over the previous generation which used DMI 2.0 – this upgrade boosts the speed from 5.0 GT/s (2GB/sec) to 8.0 GT/s (~3.93GB/sec), essentially upgrading DMI from PCIe 2 to PCIe 3, but requires the motherboard traces between the CPU and chipset to be shorter (7 inches rather than 8 inches) in order to maintain signal speed and integrity. This also allows one of the biggest upgrades to the system, chipset connectivity, as shown below in the HSIO section.

CPU Power Arrangements

Moving on to power arrangements, with Skylake the situation changes as compared to Haswell. Prior to Haswell, voltage regulation was performed by the motherboard and the right voltages were then put into the processor. This was deemed inefficient for power consumption, and for the Haswell/Broadwell processors Intel decided to create a fully integrated voltage regulator (FIVR) in order to reduce motherboard cost and reduce power consumption. This had an unintended side-effect – while it was more efficient (good for mobile platforms), it also acted as a source of heat generation inside the CPU with high frequencies. As a result, overclocking was limited by temperatures and the quality of the FIVR led to a large variation in results. For Skylake on the desktop, the voltage regulation is moved back into the hands of the motherboard manufacturers. This should allow for cooler processors depending on how the silicon works, but it will result in slightly more expensive motherboards.

A slight indication of this will be that some motherboards will go back to having a large amount of multiplexed phases on the motherboard, and it will allow some manufacturers to use this as a differentiating point, although the usefulness of such a design is sometimes questionable.

Also Launching Today: Z170 Motherboards, Dual Channel DDR4 Kits Skylake's iGPU: Intel Gen9
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  • Sttm - Wednesday, August 5, 2015 - link

    Glad to see that my 2600k is still on par for gaming; because this means I wont be tempted to buy a CPU from a company that would pay their employees $4000 not to hire someone because they have the same skin color as me, the same gender.

    Hopefully AMD will come out with a good CPU upgrade for me next year, and I can skip buying from Racist/Sexist Intel.
  • repoman27 - Wednesday, August 5, 2015 - link

    I posted this earlier, but it seems to have disappeared along with the comment it was a reply to. Is there some filtering going on in the comments section these days?

    It's annoying that Anandtech is continuing to make things confusing for everyone by deciding to call USB 3.1 SuperSpeed devices USB 3.0. We don't refer to USB 2.0 keyboards that only operate at 12 Mbit/s USB 1.0 or even USB 1.1. The problem is with the common practice of using the specification revision number as a stand-in for the maximum supported data transfer mode. Since USB's inception, their have been ordained names for the transfer modes that were supposed to be used in public facing marketing materials but everyone pretty much ignored them (Low Speed, Full Speed, High Speed, SuperSpeed, and SuperSpeedPlus).

    The USB 3.1 specification supersedes the USB 3.0 spec. Just as with HDMI, DisplayPort, or any number of other standards, not all features are required to be compliant with a given version. However, as soon as you include any feature that only appears in a newer revision, you either have to roll with that spec or be considered a non-compliant implementation.

    Using Apple as an example, although they did not include a discrete USB 3.1 host controller in the MacBook (Retina, 12-inch), they did make use of the USB Type-C Cable and Connector Specification, Billboard Device Class Specification, USB Power Delivery Specification Revision 2.0, and USB Type-C Alternate Modes including the DisplayPort Alternate Mode. While those features are all technically outside the scope of the actual USB 3.1 spec, using USB Type-C ports raises the minimum current carrying capacity to 3.0 A, which in turn requires slightly elevated VBUS voltages to account for increased losses. The VBUS supply of the new MacBook runs at up to 5.5 V DC instead of the previous limit of 5.25 V DC to ensure voltage levels are within a suitable working range at the device end. The result of this is that the USB port on the new MacBook is fully USB 3.1 compliant despite only supporting SuperSpeed or Gen 1 operation, but is not actually compliant with the original USB 3.0 specification.

    If an OEM is using USB 3.1 Gen 1 in lieu of USB 3.0 to trick people on spec sheets, then yes, it's scummy. If their implementation is such that it qualifies as USB 3.1 but not USB 3.0, then it's merely the correct way of describing it.
  • Ryan Smith - Wednesday, August 5, 2015 - link

    "I posted this earlier, but it seems to have disappeared along with the comment it was a reply to. Is there some filtering going on in the comments section these days?"

    Nope. That's my fault. I deleted the placeholder comment I had put in this morning about catching up on the graphs. I forgot that deleting a root comment also sends its children off to the void. Sorry about that.
  • Wolfpup - Wednesday, August 5, 2015 - link

    Huh. The IPC increase over Broadwell is surprisingly lame. Looking at all this, Haswell was actually a better upgrade than I’d realized.

    I’d sort of thought the team doing Conroe/Penryn/Sandy/Ivy/Skylake was better than the other team…but I guess that’s not universally true, and really Haswell is a better CPU than I’d realized. I mean not that I thought it was BAD, I just didn’t realize it was as much better over Ivy Bridge as it is.

    I’m pleasantly surprised by how big a jump there is going from Sandy Bridge to Skylake. In one thing I actually use, we’re talking about a 70% increase at the same clock speed! That’s seriously impressive, and I bet a lot of people will be upgrading from Sandy Bridge.

    I’ve got Ivy Bridge and Haswell in my main systems, and they’re certainly just fine, but it’s nice to see things are improving!

    Of course then I get to the gaming page, and…honestly it looks like if you’ve got Sandy Bridge, you’re fine, so long as you’re using a dedicated GPU.

    Kind of surprised by how decent Intel’s GPUs are now, though they still tick me off as I still want those transistors used on larger CPUs or more cores!
  • Gich - Wednesday, August 5, 2015 - link

    I'd like to change my Z68 MoBo for a Z170 while keeping my i5 2500k.
  • zlandar - Wednesday, August 5, 2015 - link

    I also do not understand why Sandy Bridge's time is "up". Who sits around running synthetic benchmarks all day? Maybe if you use your computer for alot of video processing it makes sense. The majority of people who care are going to be gamers and the bottleneck remains GPU not CPU.

    That kind of statement should be reserved for a cpu release that would make me upgrade my current system now.
  • Achaios - Wednesday, August 5, 2015 - link

    You are wrong. Yet another guy who has got no clue about gaming. There are games that depend almost completely on single threaded performance. World of Warcraft, Total War series games, Starcraft II, to name a few.

    The performance gain in those games (and other CPU bound games) over Sandy Bridge is well worth the upgrade.
  • Sttm - Wednesday, August 5, 2015 - link

    Until they get a DX12 client, at which point that CPU bottleneck evaporates.
  • Achaios - Wednesday, August 5, 2015 - link

    DX 12 will not help in Single Threaded (CPU bound) games at all.
  • mdriftmeyer - Wednesday, August 5, 2015 - link

    Nice Red Herring. No one is debating the past. They are discussing with Mantle/DirectX 12/Vulkan, those that declare themselves certified for the features touted by such will mean Single Threaded Games are of the past and moving forward implementing your DX12/Vulkan games into the core engine infers multi-core evenly distributed resource management.

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