ASIC

The design of most leading edge processors and ASICs rely on steps of optimization, with the three key optimization points being Performance, Power, and Area (and sometimes Cost). Once the architecture of a chip is planned, it comes down to designing the silicon of that chip for a given process node technology, however there are many different ways to lay the design out. Normally this can take a team of engineers several months, even with algorithmic tools and simulation to get a good result, however that role is gradually being taken over with Machine Learning methods. Cadence today is announcing its new Cerebrus integrated ML design tool to assist with PPA optimization – production level silicon is already being made with key partners as...

Marvell Announces 112G SerDes, Built on TSMC 5nm

So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14...

15 by Dr. Ian Cutress on 11/17/2020

Intel’s EMIB Now Between Two High TDP Die: The New Stratix 10 GX 10M FPGA

The best thing about manufacturing Field Programmable Gate Arrays (FPGAs) is that you can make the silicon very big. The nature of the repeatable unit design can absorb issues...

31 by Dr. Ian Cutress on 11/5/2019

Intel To Acquire eASIC: Lower Cost ASICs in FPGA Design Time

Along with the other announcement today, Intel is also announcing that it will acquire a company called eASIC which develops FPGA-like design tools to roll out ‘structured ASICs’. These...

18 by Ian Cutress on 7/12/2018

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