5nm

Samsung Foundry has made some changes to its plans concerning its 3 nm-class process technologies that use gate-all-around (GAA) transistors, or what Samsung calls its multi-bridge channel field-effect transistors (MBCFETs). Based on new information direct from Samsung, it would appear that its first version of 3nm, 3GAE (3nm gate-all-around early), is coming to high volume manufacturing a year later than expected, but also it seems to have removed this technology from its public roadmap, suggesting it may be for internal use only. Meanwhile, 3GAE's successor 3GAP (3nm gate-all-around plus) node is still in the roadmap, it is on track for volume manufacturing in 2023. 3GAE on Track for 2022, Maybe Just Not for Everyone At its recent 2021 IP & ASIC Design Ecosystem Conference in China, Samsung...

Marvell Announces OCTEON 10 DPU Family: First to 5nm with N2 CPUs

It’s been a little over a year since we covered Marvell’s OCTEON TX2 infrastructure processors, and since then, the ecosystem has been evolving in an extremely fast manner &ndash...

18 by Andrei Frumusanu on 6/28/2021

An AnandTech Interview with TSMC: Dr. Kevin Zhang and Dr. Maria Marced

In the past week, TSMC ran its 2021 Technology Symposium, covering its latest developments in process node technology designed to improve the performance, costs, and capabilities for its customers...

28 by Dr. Ian Cutress on 6/8/2021

TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022

For TSMC, being the world's largest foundry with nearly 500 customers has its peculiarities. On the one hand, the company can serve almost any client with almost any requirements...

73 by Anton Shilov on 4/26/2021

TSMC to Spend $100B on Fabs and R&D Over Next Three Years: 2nm, Arizona Fab & More

TSMC this week has announced plans to spend $100 billion on new production facilities as well as R&D over the next three years. The world's largest contract maker of...

45 by Anton Shilov on 4/2/2021

Marvell Announces 112G SerDes, Built on TSMC 5nm

So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14...

15 by Dr. Ian Cutress on 11/17/2020

Huawei Announces Mate 40 Series: Powered by 15.3bn Transistors 5nm Kirin 9000

Today Huawei took the stage to unveil the new Mate 40 series of devices. In the form of the Mate 40, Mate 40 Pro and the Mate 40 Pro+...

107 by Andrei Frumusanu on 10/22/2020

Apple Announces 5nm A14 SoC - Meagre Upgrades, Or Just Less Power Hungry?

Amongst the new iPad and Watch devices released today, Apple made news in releasing the new A14 SoC chip. Apple’s newest generation silicon design is noteworthy in that is...

127 by Andrei Frumusanu on 9/15/2020

TSMC Expects 5nm to be 11% of 2020 Wafer Production (sub 16nm)

One of the measures of how quickly a new process node gains traction is by comparing how many wafers are in production, especially as that new process node goes...

13 by Dr. Ian Cutress on 8/25/2020

TSMC Details 3nm Process Technology: Full Node Scaling for 2H22 Volume Production

At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the...

58 by Andrei Frumusanu on 8/24/2020

Intel to use Nanowire/Nanoribbon Transistors in Volume ‘in Five Years’

This year, at the international VLSI conference, Intel’s CTO Mike Mayberry gave one of the plenary presentations, which this year was titled ‘The Future of Compute’. Within the presentation...

14 by Dr. Ian Cutress on 6/22/2020

ASML’s First Multi-Beam Inspection Tool for 5nm

ASML has announced it has made a significant development in its multi-beam inspectional tool line. The new eScan1000 moves a single beam scanning process into a nine-beam scanning process...

19 by Dr. Ian Cutress on 6/1/2020

TSMC To Build 5nm Fab In Arizona, Set To Come Online In 2024

In a big shift to their manufacturing operations – and a big political win domestically – TSMC has announced that the company will be building a new, high-end fab...

100 by Ryan Smith on 5/15/2020

Updated AMD Ryzen and EPYC CPU Roadmaps March 2020: Milan, Genoa, and Vermeer

Everyone is interested in roadmaps – they give us a sense of an idea of what is coming in the future, and for the investors, it gives a level...

60 by Dr. Ian Cutress on 3/5/2020

TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles

With transistor shrinks slowing and demand for HPC gear growing, as of late there has been an increased interest in chip solutions larger than the reticle size of a...

18 by Anton Shilov on 3/4/2020

Intel CFO: Our 10nm Will Be Less Profitable than 22nm [Morgan Stanley Transcription]

This week at Morgan Stanley’s Analyst Conference, Intel’s CFO, George Davis, sat down to discuss the future of where Intel’s profitability lies. No stranger to the odd comments relating...

92 by Dr. Ian Cutress on 3/4/2020

Samsung Starts Mass Production at V1: A Dedicated EUV Fab for 7nm, 6nm, 5nm, 4nm, 3nm Nodes

Samsung Foundry has started mass production of chips using its 6LPP and 7LPP manufacturing processes at its new V1 fab. The new facility employs one of the industry’s first...

29 by Anton Shilov on 2/20/2020

TSMC Boosts CapEx by $1 Billion, Expects N5 Node to Be Major Success

TSMC is on track to begin high-volume production of chips using its 5 nm technology in the coming months, the company said in its conference call last week. While...

40 by Anton Shilov on 1/22/2020

An Interview with AMD’s CTO Mark Papermaster: ‘There’s More Room At The Top’

On the back of a very busy 2019, AMD is gaining market share and is now a performance leader in a lot of CPU segments. The company has executed...

68 by Dr. Ian Cutress on 12/30/2019

Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020

Today at the IEEE IEDM Conference, TSMC is presenting a paper giving an overview of the initial results it has achieved on its 5nm process. This process is going...

62 by Dr. Ian Cutress on 12/11/2019

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