While the first 3D NAND chips have just found their way to the market and most NAND manufacturers are still developing their designs, there are already a handful of next generation memory technologies in development that are slated to supersede NAND in the next decade or so. One of the most promising technologies is Resistive Random Access Memory, which is more commonly referred to as Resistive RAM or just RRAM. Similar to NAND, RRAM is non-volatile, meaning that it will retain data without power unlike regular DRAM, which needs a continuous power source. Multiple companies are developing RRAM including semiconductor giants like Samsung and SanDisk, but Crossbar, a US based startup, has probably the most advanced design so far.

I've been following Crossbar for quite some time, but I haven't written anything about the company until now. The company was founded in 2010, headquarters in Santa Clara, California and has secured over $50 million in funding. The company's roots come from the University of Michigan and its Chief Scientist and co-founder, Prof. Wei Lu, is currently an associate professor at the university. The Crossbar team consists of 40-45 members at this point, of which most have extensive backgrounds in semiconductor research and development. 

The big benefits RRAM have over NAND are performance and endurance. NAND read latencies are typically in the order of hundreds of microseconds, whereas Crossbar claims latency of as low as 50 nanoseconds for its RRAM design. Endurance in turn can be millions of program/erase cycles, although for the early designs Crossbar is aiming at more conservative ~100K cycles. 

Last week at IEDM Crossbar announced that it is now entering the commercialization stage. In other words, it has already shown a working silicon and it has also proved that the design can be transferred to commercial fab for high volume manufacturing, so the company is now working with the fabs to build final products.

At first Crossbar is aiming at the embedded market and is licensing its technology to ASIC, FPGA and SoC developers with first samples arriving in early 2015, and mass production scheduled for late 2015 or early 2016. Aside from licensing, Crossbar is also developing standalone chips with higher capacity and density, which should enter the market about a year after the embedded RRAM designs (i.e.most likely sometime in 2017).

The beauty of RRAM is that it can be manufactured using a regular CMOS process with only a few modifications. NAND and especially 3D NAND require expensive special tools (for things like high aspect ratio etching), which is why only a handful of companies are making 3D NAND. RRAM in turn can be manufactured by practically any existing fab with very little added cost, which ultimately results in lower prices due to more competition.

Additionally, RRAM doesn't share NAND's lithography issues. As we know, the sole reason why 3D NAND was invented is because planar NAND can't really scale below 15nm without serious endurance and performance considerations. However, RRAM can efficiently scale to 4-5nm without any issues and in fact Crossbar has already demonstrated an 8nm chip that it built in its R&D labs (most likely using multiple patterning). Moreover, RRAM can be stacked vertically to create a 3D crosspoint array for increased density and so far Crossbar is at three layers, but first commercial standalone chips are expected to feature 16 layers and up to 1Tbit capacity. 

Obviously, there are still several hurdles to cross before RRAM is ready to challenge NAND, but it's good to hear that there has been significant progress in development and the technology has gained interest from the fab companies. Faster, more durable and cheaper SSDs and other storage devices are a win for everyone and ultimately even 3D NAND is just an interim solution until something better comes around, which may very well be RRAM. I'll be doing a more in-depth article about RRAM technology in the coming months as this article was more of a heads up about the state of RRAM and Crosspoint's recent developments, so stay tuned for a deeper analysis!

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  • iwod - Monday, December 22, 2014 - link

    Thx, Looking forward to it. I guess the processing overhead of RRAM will be much much smaller compared to NAND if those features aren't needed by the controller. Reply
  • FunBunny2 - Monday, December 22, 2014 - link

    -- which means that there is practically no need for garbage collection and wear-leveling.

    I don't see wear leveling not needed. Less, may be, but not not.
    Reply
  • Guspaz - Monday, December 22, 2014 - link

    Wear levelling implies a performance impact, since part of effective wear levelling is moving previously written data around to expose lower-cycle blocks. When you're talking about 100 million cycles or more, wear levelling isn't really important anymore. If you assume 4KB blocks (even if RRAM isn't block-based, the underlying filesystem will be), you're talking about writing 400 gigabytes to a single block before you'd have to start worrying about wear. At those kinds of endurances, you can effectively assume that there is no cycle limit at all. Reply
  • FunBunny2 - Monday, December 22, 2014 - link

    -- for the early designs Crossbar is aiming at more conservative ~100K cycles.

    Not to mention leakage and such.
    Reply
  • tuxRoller - Wednesday, December 24, 2014 - link

    Using a regular fs on this type of device doesn't make much sense. FSs are designed around constraints which aren't present for this type of device.
    I know the linux community has been discussing what such a fs should look like. New apis will need to be created.

    http://lwn.net/Articles/547903/
    Reply
  • Gigaplex - Friday, December 26, 2014 - link

    "Using a regular fs on this type of device doesn't make much sense."

    Under Windows, there's pretty much only one option for file systems. They're not going to move away from NAND to RRAM if the SSDs don't work on Windows.
    Reply
  • Jaybus - Saturday, January 3, 2015 - link

    In many ways, a "regular" fs isn't a good fit for NAND either. To compensate, low level features such as trim were inserted into existing the existing fs. On the other hand, there are existing paradigms utilizing traditional fs's that could more readily match RRAM. Memory-mapped i/o is a perfect fit. But this requires application software rewrites and will take time. Reply
  • JonnyDough - Wednesday, December 24, 2014 - link

    "Wear levelling implies a performance impact, since part of effective wear levelling is moving previously written data around to expose lower-cycle blocks"

    Not necessarily, if it is done in the background when nothing is being read or written to the drive and all cores/cycles of the processor are not in use. It's just a matter of properly written firmware and OS's.
    Reply
  • FunBunny2 - Wednesday, December 24, 2014 - link

    -- Not necessarily...

    It is generally agreed that, once a threshold level is filled, an SSD will stall on GC, wear leveling, and general NAND management. One trick often used is to increase spare area, thus delaying reaching the threshold and leaving more scratch space to do the management.

    But yes, if RRAM/etc. behave like NOR (byte addressable) and r/w, then we have a winner. .
    Reply
  • extide - Monday, December 22, 2014 - link

    Seems like you would still need wear leveling, as there is a limited endurance (although it is quite high) -- but not the whole garbage collection and trim stuff that we have now.

    Although, I still see having trim as a good thing for enterprise storage as for example when using thin provisioned storage it can actually release blocks for use in something else, instead of now where one a block is written to it is used forever, or at least until that image or volume is deleted.
    Reply

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