TSMC this week announced a new fabrication process that is tailored specifically for high-performance computing (HPC) products. N4X promises to combine transistor density and design rules of TSMC's N5-family nodes with the ability to drive chips at extra high voltages for higher frequencies, which will be particularly useful for server CPUs and SoCs. Interestingly, TSMC's N4X can potentially enable higher frequencies than even the company's next-generation N3 process.

One of the problems that is caused by shrinking sizes of transistors is shrinking sizes of their contacts, which means increased contact resistance and consequent problems with power delivery. Various manufacturers use different ways of tackling the contact resistance issue: Intel uses cobalt contacts instead of tungsten contacts, whereas other makers opted to forming contacts using selective tungsten deposition technology. While these methods work perfectly for pretty much all kinds of chips, there are still ways to further improve power delivery for high-performance computing (HPC) designs, which are relatively immodest about the total about of power/voltage being used. This is exactly what TSMC did to its N4X node. But before we proceed to details about the new fabrication process, let us see what advantages TSMC promises with it. 

TSMC claims that its N4X node can enable up to 15% higher clocks compared to a similar circuit made using N5 as well as an up to 4% higher frequency compared to an IC produced using its N4P node while running at 1.2V. Furthermore – and seemingly more important – N4X can achieve drive voltages beyond 1.2V to get even higher clocks. To put the numbers into context: Apple's M1 family SoCs made at N5 run at 3.20 GHz, but if these SoCs were produced using N4X, then using TSMC's math they could theoretically be pushed to around 3.70 GHz or at an even higher frequency at voltages beyond 1.2V.

TSMC does not compare transistor density of N4X to other members of its N5 family, but normally processors and SoCs for HPC applications are not designed using high-density libraries. As for power, drive voltages of over 1.2V will naturally increase power consumption compared to chips produced using other N5-class nodes, but since the node is designed for HPC/datacenter applications, its focus is to provide the highest performance possible with power being a secondary concern. In fact, total power consumption has been increasing on HPC-class GPUs and similar parts for the last couple of generations now, and there is no sign this will stop in the next couple of generations of products, thanks in part to N4X.

"HPC is now TSMC's fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies," said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. "The demands of the HPC segment are unrelenting, and TSMC has not only tailored our ‘X’ semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric advanced packaging technologies to offer the best HPC platform."

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
  TSMC
N5
vs
N7
N5P
vs
N5
N5HPC
vs
N5
N4
vs
N5
N4P
vs
N5
N4P
vs
N4
N4X
vs
N5
N4X
vs
N4P
N3
vs
N5
Power -30% -10% ? lower -22% - ? ? -25-30%
Performance +15% +5% +7% higher +11% +6% +15%
or
more
+4%
or more
+10-15%
Logic Area

Reduction %

(Density)
0.55x

-45%

(1.8x)


-


-
0.94x

-6%

1.06x
0.94x

-6%

1.06x


-


?


?
0.58x

-42%

(1.7x)
Volume
Manufacturing
Q2 2020 2021 Q2 2022 2022 2023 H2 2022 H1
2024?
H1 2024? H2 2022

In a bid to increase performance and make drive voltages of over 1.2V possible, TSMC had to evolve the entire process stack.

  • First, it redesigned its FinFET transistors and optimized them both for high clocks and high drive currents, which probably means reducing resistance and parasitic capacitance and boosting the current flow through the channel. We do not know whether it had to increase gate-to-gate pitch spacing and at this point TSMC does not say what exactly it did and how it affected transistor density.
  • Secondly, it introduced new high-density metal-insulator-metal (MiM) capacitors for stable power delivery under extreme loads.
  • Thirdly, it redesigned back-end-of-line metal stack to deliver more power to transistors. Again, we do not know how this affected transistor density and ultimately die sizes.

To a large degree, Intel introduced similar enhancements to its 10nm Enhanced SuperFin (now called Intel 7) process technology, which is not surprising as these are natural methods of increasing frequency potential.

What is spectacular is how significantly TSMC managed to increase clock speed potential of its N5 technology over time. A 15% increase puts N4X close to its next-generation N3 fabrication technology. Meanwhile, with drive voltages beyond 1.2V, this node will actually enable higher clocks than N3, making it particularly good for datacenter CPUs.

TSMC says that expects the first N4X designs to enter risk production by the first half of 2023, which is a very vague description of timing, as it may mean very late 2022 or early 2023. In any case, it usually takes a year for a chip to proceed from risk production to high-volume production iteration, so it is reasonable to expect the first N4X designs to hit the market in early 2024. This is perhaps a weakness of N4X as by the time its N3 will be fully ramped and while N4X promises to have an edge in terms of clocks, N3 will have a major advantage in terms of transistor density.

Source: TSMC

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  • brucethemoose - Friday, December 17, 2021 - link

    Server CPUs are still clocked relatively high, just not at nutty frequencies like today's desktop chips. I bet they're in the part of the voltage/frequency curve where they would benefit from this process. Reply
  • evanh - Saturday, December 18, 2021 - link

    Relative being a comparative term, doesn't that imply that servers have to be on the low side when compared to other general computing?

    I'm still under the impression that HPC is different to data-centre servers. Is that no so?
    Reply
  • Kevin G - Saturday, December 18, 2021 - link

    HPC can use commodity server hardware and networking if cost is a dominant factor. HPC so about tuna the server hardware toward maximize performance and do the scaling by the cluster size. Server clusters are generally in the single digits to cover for redundancy but each node has flexibility for the variety of server workloads and expansion.

    HPC can go a bit higher in terms of raw power per node and they get the funding to use exotic networking and cooling. They are still power limited like servers but where they allocate power to in the design and handle it is just different.

    Probably the biggest differentiator is that servers favor two (or more when possible) DIMMs per channel. This eats up a bit of power and lower performance a tad but the user get more memory in a system. The HPC side will focus on one DIMM per channel to focus on higher memory clocks and lower latency rather than capacity. Networking is also different has HPC is both latency and bandwidth focused. Traditional servers are more commodity Ethernet focused that has increasingly focused on virtualization and legacy scaling (ie a new server has to be on the same network as a decade old app server that can’t go down).
    Reply
  • eldakka - Saturday, December 18, 2021 - link

    > As far as I was aware, your typical web/file server is all about power efficiency.

    Data Centre does not mean web/file servers. Sure, those are components of it, but, for example at my work, we have database servers running on PPC hardware using scores of cores (for single instances, we have many instances useing several hundred PPC cores all up). A transaction may require a lot of database work, and you want that to complete in 1/2 second no matter whether it's a simple select from a single indexed table, or involves multiple joins across several multi-billion-row tables, and SQL statements that are 20 lines long.

    There's a lot of biometrics in there, matching images, etc., all which again you want to complete in 1/2 second or less.

    No, there is a lot of high performance operations and hardware in data centres that might not be scientific HPC (weather modelling, universe simulations, mass brute-force decryption, etc.), but there is still plenty of high performance required.
    Reply
  • KurtL - Saturday, December 18, 2021 - link

    High-performance computing is different and not different from running typical web/file servers. True supercomputing is all about cost efficiency and hence also power efficiency. It's really hard these days to argue that yo u need an infrastructure that uses millions of dollars of power per year these days. Reaching exascale is all about doing it at as reasonable power levels as possible. HPC is of course different from running web servers as depending on the application there is often a need for fast high-precision floating point computations, or for AI Inference, fast vector and matrix math on short datatypes. And it is also different because the thousands of processor chips have to be able to communicate with each other with as low latency as possible.

    Truly the only market in datacenters where high frequencies at any power level are acceptable, is for those applications that don't scale to a distributed memory model and need a single OS image, or even don't scale well to multiple cores and need as high single thread performance as possible.

    The N4X process really seems more useful to me for gaming PCs and workstation replacements (which would then be operated remotely as the cooling of such high power beasts is way too noisy for an office) than many datacenter or supercomputer applications.
    Reply
  • ballsystemlord - Friday, December 17, 2021 - link

    How do they cool the chip with all that extra power running through it? Even AMD's current 7nm generation are thermally limited because of the density. Reply
  • ballsystemlord - Friday, December 17, 2021 - link

    PS: For those who've not been following discussions of this sort. The Silicon is currently thermally limiting the amount of heat that can be dissipated at 7nm. At N4X (4nm) it will be worse. Reply
  • Alistair - Friday, December 17, 2021 - link

    they are not thermally limited at all, clearly you don't own one... Reply
  • Wrs - Saturday, December 18, 2021 - link

    5800x here, was thermally limited at just under 125w on the CCD, using a D15 air cooler. Samples do vary but there are plenty of 5900x/5950x that suffer the same; it's just hidden when a synthetic benchmark spreads the load among two CCDs. Mind you we're talking 1.5 watts/mm2, and when the die area expands that limit drops to converge on the one dimensional thermal design limit. Compare to existing N5 chips typically running 0.25 watts/mm2. Reply
  • Alistair - Saturday, December 18, 2021 - link

    that's totally not true, I have a 5800x with a noctua U12, there is something seriously wrong with your mounting or your cooler

    150W on the U12 even, is fine
    Reply

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