Intel Launches 10nm Atom Embedded CPUs: Elkhart Lake Now Availableby Dr. Ian Cutress on September 23, 2020 9:00 AM EST
The embedded and edge markets for Intel have always been hidden away within its IoT business, however at the Investor Meeting last year it was highlighted as one of Intel’s key growth areas. The requirements for businesses to enable automation and control, as well as apply machine learning or computer vision, have increased as new optimized algorithms and use cases enter the market, and this is the question that the new 10nm Atom Embedded CPUs are set to answer.
Elkhart Lake built upon Tremont with 10nm
The new processors built with Tremont Atom cores will come as three series of processors: Pentium, Celeron, and Atom x6000E. These are all built with the same silicon die, offering up to four Atom cores with a 3.0 GHz turbo frequency, up to 850 MHz of Gen11 graphics (up to 32 EUs, three 4K60 displays), in TDPs ranging from 4.5 W to 12 W. All processors will support up to LPDDR4X-4267 or DDR4-3200. In-band ECC support is split - the Atom x6000E parts have it, but the Pentium and Celerons do not.
|Intel Elkhart Lake
Tremont Atoms for Embedded
|Pentium J/N and Celeron J/N|
|Atom x6000RE: RTOS Support|
|Atom x6000FE: Intel Safety Island Support|
|* Has no IGP|Intel is also moving to 10nm SuperFin (formerly 10++) for its Atom nodes, making these the next 10nm-class Atom processors after Intel’s Snow Ridge for 5G networks.
Intel has since updated and told us that these products use the same 10nm process as Ice Lake.
Focusing on IoT Features
Previous embedded processors like this were perhaps not always focused with the Edge market or the IoT market in mind. This time around however, Intel states that these products have been built from the ground up with this market in mind. This lends itself to a number of IoT-specific features.
There is now a new Programmable Services Engine to offload IoT workloads. This is a dedicated ARM processor, specifically an Arm Cortex M7, that supports real-time functionality, network synchronization, time sensitive networking, and low compute requirement workloads without needing to fire up the bigger cores. Some of the models support Time Coordinated Computing to enable worst-case execution time (WCET) and ultra-reliable low-latency communication (URLLC)
Two processors, the Atom x6427FE and x6200FE, are FuSa certified and support Intel’s Safety Island technology to allow integrated functional safety within IP blocks for finding and flagging faults, as well as initiating internal diagnostic tests.
All of these CPUs have three integrated 2.5 GbE MACs, all of which can be enabled for time-sensitive networking. The cores have Intel’s SHA extensions, as well as AES-NI and Intel Secure Key. Note that Intel is the only x86 vendors who does not have SHA-acceleration hardware, instead deciding to rely on instruction-level optimization.
The new processors all support Intel’s OpenVINO toolkit, with pre-optimized libraries for AI, ML, and computer vision acceleration. This is on top of Intel’s new Edge Software Hub, an interface for OEM customers to acquire pre-optimized deployment-ready software packages optimized for Industrial, Retail and Vision, all of which also offer customizability.
OS support is listed as Windows 10 IoT Enterprise, Yocto Project BSP, Linux Ubuntu, Wind River Linux LTS, and Android 10. The boot firmware supports Intel Slim Bootloader as well as coreboot, and the Programmable Services Engine runes on Intel’s own Zephyr RTOS-based platform.
For performance, Intel is claiming 1.7x single thread over two-generation old Apollo Lake Atoms, and 1.5x in multi-threaded workloads. Graphics performance gen-on-gen is listed as 2x. These numbers come from SPEC2006int and 3DMark11, but are based on pre-silicon projections of the new hardware (and it seems odd it wasn't compared to the Gemini Lake hardware). This would suggest that Intel doesn’t have the silicon in the labs yet to run the tests, which is a little odd if this is the launch day. Nonetheless, these platforms have a 7+ year lifecycle.
Intel confirmed that the CPU-to-PCH connection is not DMI in this instance, but just OPIO. The chipset will support eight lanes of PCIe 3.0, four USB 3.1 ports, ten USB 2.0 ports, and two UFS 2.0 ports.
For package, Intel stated that all models will be FCBGA1493 and measure 35x24mm. Interestingly enough, this means we can calculate estimates for the die size.
- CPU die (left): 9.169 mm * 6.394 mm = 58.63 mm2
- PCH die (right): 6.369 mm * 9.778 mm = 62.27 mm2
The CPU is built on 10nm Superfin, the PCH die is built on 14nm. Note that in our recent review of the Tiger Lake UP3 processor, the PCH die for that processor with callipers was measured at 56.4 mm2. Given the rough nature of how we calculate these things, I might be inclined to believe that this mockup of Elkhart Lake might simply be the PCH die rotated and changed slightly, rather than a true-to-life example of the processor.
There's no word from Intel when these might be coming to low-power consumer products. Being built on 10SF, I suspect that the die cost might be higher than what we're normally used to. These new parts were announced as part of Intel's Industrial Summit, and as such these product managers wouldn't necessarily know what the client division would be preparing with the same silicon.
But Wait, There’s More!
Intel isn’t only announcing these new 10nm Atoms today. For the embedded applications that need more performance, there will be versions of the Tiger Lake UP3 mobile processors also for embedded markets. These are the same as the client versions of the processors, however with lower peak turbo frequencies. There will be a focus on enabling industrial workloads though the Xe graphics, AVX-512 units, and onboard neural accelerators. Real Time Computing will be enabled on the Industrial parts.
|Intel Core Embedded CPUs
|i3-1115GRE||2C/4T||1700||3900||48||Yes||12-28W||-40-100|All three are also offered with In-Band ECC and a -40ºC to 100ºC temperature window, however these have the same SKU names as the ones we've already listed. Just to confuse things.
Update: Turns out the documents we were given ahead of the launch had a number of typos in the specifications. The article has been updated.
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