Blink and you miss it: AMD's keynote address this year was a whirlwind of primetime announcements for the company. The message is clear: AMD is committing itself to 7nm as the future process node that will drive the company's innovations starting in 2019. The first consumer products on 7nm will be the Ryzen 3rd Generation Desktop processors, using Zen 2 cores, offering more than competitive performance against Intel's best hardware. Also on the docket is a return to high-end graphics performance, with AMD set to release a 7nm graphics card that can spar blow-for-blow with the competition at the $700 price barrier.

AMD at CES 2019

One of the odd things about AMD’s announcements this show has been the tale of two halves. Normally a company will push out single major press release with everything in it. This year AMD discussed its news around Ryzen-3000 series mobile parts and AMD Chromebooks just as the show started, and we were all confused if this was going to constitute what was in the keynote or not – it would seem odd, after all, for the company to pre-announce its keynote announcements. Luckily, AMD has plenty to announce, and it’s all pretty juicy.

First up, CPUs. AMD presented its next generation 7nm desktop CPU, which is the 3rd Generation Ryzen.

Attacking the Mainstream CPU Market: Toe to Toe with Core i9-9900K

Ignore everything you might have heard about what AMD’s future desktop CPU is going to be. Here are most of the details you need to know.

The new parts, codenamed Matisse, will be coming to market in mid-2019 (sometime in Q2 or Q3). The processor the company had on display was made from two pieces of silicon on the package: one eight-core 7nm chiplet made at TSMC, and a 14nm input/output chiplet with the dual memory controllers and the PCIe lanes, made at GlobalFoundries.

The company did state that it is the world’s first 7nm gaming CPU, and will also be the world’s first mainstream CPU to support PCIe 4.0 x16. At this time the company is not commenting on if the 3rd Gen is going to have a maximum of eight cores, or if this represents the best processor of the whole family.

Because the processor is still far away from launch, frequencies are not being finalized yet. However, the processor is for the AM4 socket, given that AMD has previously said that it intends to keep backwards compatibility for several generations. That will mean that this CPU will work in current 300 and 400-series AMD motherboards.

What this means for PCIe 4.0 is actually fairly simple. We expect there to be a new line of motherboards presumably something like X570 that will be PCIe 4.0 compatible, for any new PCIe 4.0 graphics cards that will be coming to market. One of the differences with PCIe 4.0 is that it can only handle PCB traces up to 7 inches before needing a redriver/retimer, so these extra ICs are needed for ports lower down the board. But, the first PCIe slot on most motherboards is in that limit, so it would appear that a lot of current 300 and 400 series motherboards, assuming the traces adhere to signal integrity specifications, could have their first PCIe slot rated at PCIe 4.0 with new firmware.

Going For Die Size

As we can see on the die shot above, the 8-core chiplet is smaller than the IO-die, similar to the 8+1 chiplet design on EPYC. The IO-die is not exactly one quarter of the EPYC IO-die, as I predicted might be the case back the Rome server processor announcement launch, but it is actually somewhere between one quarter and one half.

Doing some measurements on our imagery of the processor, and knowing that an AM4 processor is 40mm square, we measure the chiplet to be 10.53 x 7.67 mm = 80.80 mm2, whereas the IO die is 13.16mm x 9.32 mm = 122.63 mm2.

+15% Performance Generation on Generation, Minimum.

During the keynote, AMD showed some performance numbers using the new Ryzen 3rd Generation (Matisse) processor. The test in question was Cinebench R15.

Our internal numbers show the 2nd Generation Ryzen 7 2700X scores 1754.

This new 3rd Generation Ryzen processor scored 2023.

This would mean that at current non-final clocks, the new parts give a 15.3% increase in performance generation on generation. Cinebench is an idealized situation for AMD, but this is not at final clocks either. It will depend on the workload, but this is an interesting data point to have.

Identical Performance to the Core i9-9900K, Minimum.

Our internal benchmarks show the 9900K with a score of 2032.

The 8-core AMD processor scored 2023, and the Intel Core i9-9900K scored 2042.  

Both systems were running on strong air cooling, and we were told that the Core i9-9900K was allowed to run at its standard frequencies on an ASUS motherboard. The AMD chip, by contrast, was not running at final clocks. AMD said that both systems had identical power supplies, DRAM, SSDs, operating systems, patches, and both with a Vega 64 graphics card.

At Just Over Half The Power…?!

Also, in that same test, it showed the system level power. This includes the motherboard, DRAM, SSD, and so on. As the systems were supposedly identical, this makes the comparison CPU only. The Intel system, during Cinebench, ran at 180W. This result is in line with what we’ve seen on our systems, and sounds correct. The AMD system on the other hand was running at 130-132W.

If we take a look at our average system idle power in our own reviews which is around 55W, this would make the Intel CPU around 125W, whereas the AMD CPU would be around 75W.

AMD Benchmarks at CES 2019
AnandTech System Power Idle Power* Chip Power CB 15 MT Score
CB 15 MT Score
All-Core Frequency
AMD Zen 2 130W 55W 75W 2023 2057 ?
Intel i9-9900K 180W 55W 125W 2042 2040 4.7 GHz
*A rough estimate given our previous review testing

This suggests that AMD’s new processors with the same amount of cores are offering performance parity in select benchmarks to Intel’s highest performing mainstream processor, while consuming a lot less power. Almost half as much power.

That is a powerful statement. (ed: pun not intended)

How has AMD done this? IPC or Frequency?

We know a few things about the new Zen 2 microarchitecture. We know it has an improved branch predictor unit, and improved prefetcher, better micro-op cache management, a larger micro-op cache, increased dispatch bandwidth, increased retire bandwidth, native support for 256-bit floating point math, double size FMA units, and double size load-store units. These last three parts are key elements to an FP-heavy benchmark like Cinebench, and work a lot in AMD’s favor.

As the Intel CPU was allowed to run as standard, even on the ASUS board, it should reach around 4.7 GHz on an all-core turbo. AMD’s frequencies on the processor were unknown; but also they are not final and we ‘should expect more’. Well, if the processor was only running at 75W, and they can push it another 20-30W, then there’s going to be more frequency and more performance to be had.

The one thing we don’t know is how well TSMC’s 7nm performs with respect to voltage and frequency. The only chips that currently exist on the process are smartphone chips that are under 3 GHz. There is no comparable metric – one would assume that in order to be competitive with the Core i9-9900K, the processor would have to match the all-core frequency (4.7 GHz) if it was at the same IPC.

If the CPU can't match IPC or frequency, then three things are possible:

  1. If the TSMC process can’t go that high on frequency, then AMD is ahead of Intel on IPC, which is a massive change in the ranks of modern x86 hardware.
  2. If the TSMC process can clock above 5.0 GHz, AND there is room to spare in the power budget to go even higher, then it’s going to be really funny seeing these processors complete.
  3. AMD's Hyperthreading for software such as CineBench is out of this world.

TL;DR = AMD’s 3rd Gen Ryzen Processors Are Another Step Up

When speaking with AMD, their representative said that there will be more information to follow as we get closer to launch. They’re happy for users to discuss whether it is IPC or frequency that is making AMD the winner here, and they’ll disclose more closer to the time.

Ian, I Thought You Predicted Two Chiplets?

Naturally, I assumed that AMD would be presenting a Ryzen-3000 series desktop processor with sixteen cores. For me, and a lot of others, felt like a natural progression, but here we are today with AMD only mentioning an eight core chip.

I predicted wrong, and I've lost my money (ed: in Las Vegas no less). But if we look at the processor, there’s still room for a surprise.

There’s room for a little something extra in there. There’s not much room for a little something extra, but I’m sure if AMD wanted to, there’s just enough space for another CPU chiplet (or a GPU chiplet) on this package. The question would then be around frequency and power, which are both valid.

There's also the question of lower core count processors and the cheaper end of the market. This processor uses silicon from TSMC, made in Taiwan, and GlobalFoundries, made in New York, then packaged together. We have heard some discussion from others not in the industry that this makes cheaper processors (sub $100) less feasible. It is entirely possible that AMD might address that market with future GPU. 

What AMD has plans for in the future, I don’t know. I don’t have a crystal ball. But it does look like AMD has some room to grow in the future if they need to.

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  • ajc9988 - Wednesday, January 9, 2019 - link

    Ian, you didn't loose your money yet. There are traces to the second spot you point out on the PCB (hard to see in your photo, but I could see them at certain angles when Su held it up during the keynote). For latencies, since they are using the I/O die like on the Epyc CPU, they are able to mask the NUMA element so the entire package is a single NUMA node. That avoids the pitfalls of NUMA node issues we saw with first and second gen TR and first gen Epyc.

    That space will be filled by release, I could guarantee that. Meanwhile, the IF2 controller and higher bandwidth, lower latencies of second gen Infinity Fabric will be present. In fact, the latency of going off die for every memory call will already be found by doing the I/O die with IF2, so please ask questions on the IF2 latency. Meanwhile, that means accessing the cache on the second die, since it was mentioned Epyc has it fully routed through the I/O die, will require the additive latency of going all the way round trip, 2 hops each way, unless they are using the enlarged L3 cache to be mirrored between the two chips, with some way setup to sync them and retire the data relatively to each other. That might be why the L3 was enlarged that much. So many more questions.

    But don't pay up until after the release.

    Also, with the cache on the active interposer for Foveros, likely L3 shared cache feeding the L2 for both the bigLITTLE cores, I have to also say I'm very impressed with the 3D stacking Intel is doing. I crapped on their statements last month and need to eat my words there, just as an aside.
  • AlexDaum - Wednesday, January 9, 2019 - link

    I could see that they do not have a shared L3$ between chiplets, but rather some kind of L4$ in the I/O die. I would think it would make sense to have that L4$ as kind of memory bandwidth saving method, so that when two chiplets require the same data, it is already in L4 after the first fetch, but the CPUs don't have to talk to each other to first see if any L3 contains that data... Kind of the same as between L2$ per core and L3$ shared, the cores don't look into other L2$ to figure out if they have the data, they just look in L3, and if it misses, then it gets fetched from memory.
  • GreenReaper - Wednesday, January 9, 2019 - link

    They could mask the NUMA configuration, but it probably wouldn't be a great idea in general. It's useful information to have, if only the operating system uses it properly.
  • KOneJ - Wednesday, January 9, 2019 - link

    They can't bank on that with Windows though.
  • rocky12345 - Wednesday, January 9, 2019 - link

    I am actually ok with it just being 8 core and if it is 8 cores on a single die even better. From the looks of the CPU and the space left it does look like they left themselves the option to either add another chiplet if needed or this is not the top end chip and we just might be seeing a 10 or 12 or 16 core CPU as well. I myself plan on just going for the 8/16 CPU when they launch. If they do indeed release a 10 or 12 core part I might look into that as well but if adding a second Chiplet adds latency and causes games to have less FPS then I will just stick with the 8/16 CPU which is more than enough for me anyway.
  • JKJK - Wednesday, January 9, 2019 - link

    This is great!! I'm planning a pcie4.0 build (hedt) and seeing how these cpus will perform and how Intel will answer is so fucking exciting! I CAN'T WAIT!!! :D
  • Rakman - Wednesday, January 9, 2019 - link

    Ian Cutress, you can't "pre-announce" anything. You either announce it, or you do not announce it. There is no other status of announcing. "Pre" means "before", as in a sports pre-game show that occurs before the game that it announces. You can "early announce" something, but that is still an announcement. You also violated one of the rules of logic. Something cannot be both A and B at the same time and in the same context.
  • KOneJ - Wednesday, January 9, 2019 - link

    They didn't announce the SKUs with a launch date. They did demo the hardware though, before announcement. I don't think the pre-announcement phrasing was at all egregious. It's fair to call it a pre-announcement demo as they weren't announcing final products for sale.
  • mkaibear - Thursday, January 10, 2019 - link

    Sorry, that's incorrect.

    You can easily "pre-announce" something. If I say "we have a new product coming up, we're not going to announce final clock speeds or configs yet but here's some info" that meets all the criteria for not announcing something but nevertheless providing information on it. Hence pre-announce.
  • GreenReaper - Thursday, January 10, 2019 - link

    That's still announcing that there will be more information later.

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