When AMD announced it was creating the new high-performance Zen core, they set a lofty goal. They wanted to produce products that offered 25x the relative efficiency (performance per watt) between 2014 and 2020. This was called the 25x20 goal, and AMD gave an update.

Starting from a baseline of Kaveri, AMD has put the Ryzen Mobile processors currently at 5.86x the performance efficiency in 3 years. That leaves another ~5x performance to get in the next three years. That’s a steep hill to climb, and it is clear that the scale of the graph above seems to be wrong, with Ryzen Mobile being half-way up the graph, rather than around 20% up the graph. If AMD is set to make that target, then they are expecting a huge jump in efficiency coming up. Is that what Navi is?

For this data, AMD also gave some insight into how they are calculating it. In the footnotes, we get the following steps:

  1. Overall performance efficiency is C divided by E
  2. Performance is a 50:50 average of CPU and GPU performance (variable ‘C’) compared to Kaveri
    - CPU Performance from Cinebench 15 Multi-Threaded
    - GPU Performance from 3DMark 11 P
  3. Energy Use (variable ‘E’) defined by ETEC ‘Typical Energy Consumption from Notebooks’ as per Energy Star Program Requirements Rev 6.1 Oct-2014
  4. Kaveri is the Baseline where C/E = 1.00x

To calculate C, the following equation is used:

So say for example the base processor scored 100 in Cinebench and 1000 in 3DMark 11. If the upgraded processor scored 150 and 2000, the overall value of C would be 0.5 x (150/100 + 2000/1000) = 1.75.

To calculate C, we have to go to the Energy Star documents and pull out this long equation:


The PT(x) options are the power consumed in those modes multiplied by a given weighting factor in the document listed above. But it is worth noting that because it involves system level power in off/sleep/idle states, it is also subject to any efficiency improvements from the other component manufacturers as well, such as DRAM, IO, power delivery and display. Part of the goal here is performed by the vendors, not AMD.

AMD provided all the benchmark data for the CPU and GPU parts, as well as ‘overall’ values for E. These are all taken from mobile APU parts.

AMD's 25x20 Goal: Progress
R15 nT
3DMark 11 P Variable C Variable E Performance
Raven Ridge 719 4315 2.56 0.44 5.86x
Bristol Ridge 279 3234 1.36 0.34 3.97x
Carrizo 277 2709 1.23 0.35 3.51x
Kaveri 232 2142 1.00 1.00 1.00x

From the table, we can clearly see that moving from Kaveri to Carrizo was mainly about the power consumption under the Energy Star test, moving the denominator to a nice low number. Moving from Carrizo to Bristol Ridge was about GPU performance, extracting the most out of the 28nm process for frequency at the same power and some better binning.  The jump to Raven Ridge/Ryzen Mobile marks a big step for Cinebench, given the new high-performance core, and a bump in 3D Mark performance.

What is interesting to note is that the variable ‘E’ has gone up from Bristol Ridge to Raven Ridge, from 0.34 to 0.44.  This is despite AMD claiming a 58% power reduction in workloads like Cinebench. This will be down to how the Energy Star guidelines are set out, which in this instance do not favor how a system is applying the power (regardless of performance).

It brings up how AMD is going to achieve its 25x goal by 2020. Ryan and I discussed this at length before I wrote this segment, but there are a few interesting things to note.

Calculating E: It's in the System

In order to calculate E, AMD relies on a good representation of the whole system, not just the processor. That includes things like memory, the display, and other components. This means that the improvements in these segments should help significantly towards that goal. One major thing that AMD could do with the next generation is swap support for DDR4 to either LPDDR3 or LPDDR4. The reason why is the low power states.

When we asked why AMD is not supporting LPDDR memory on Ryzen Mobile, the response was related to performance. If we look at almost every single Intel 15W notebook on the market, despite the processors supporting both LPDDR3 and DDR4, they all use LPDDR3 by default. If we ask the OEMs, the answer lies in the power consumption during lower power modes such as idle: LPDDR memory can achieve much, much lower power modes than standard DDR. We put this to AMD and they looked confused, saying that literally none of their OEM partners had ever brought this up in conversation as a requirement for a future platform.

Nonetheless, that value of E could take a nice tumble when AMD implement LPDDR on a future APU. I’d bet some money on that being the case.

Process Nodes Matter

Ryan also pointed out that AMD could implement a super low power SKU, something like Intel’s Core-M line that sits at 4.5W. At that low power, the value for E should be cut considerably. However, we have to think if these parts actually have a lower idle/off power than Intel’s 15W, or if it is, in fact, all in the binning. They would certainly have lower VRM losses by having fewer VRMs in play anyway. This is something AMD could pursue, assuming the performance values could be kept high.

We are also expecting AMD to implement GlobalFoundries 7nm process before 2020. That should yield a number of improvements for power, especially if AMD decides to fab a chip on a low power node.

The Future of Performance

On the C side of the equation, more is better. There are still a couple of iterations in the public roadmap for Zen from now until 2020, so the CPU performance could increase another 10-25%. Moving to 7nm could also lend itself to doubling the core count, giving a sizeable increase in the Cinebench or 3DMark score. With extra transistors and new GPU architectures (like Navi, or beyond), there is room to grow.

We did some mockup numbers to see where AMD would sit. The new 25x20 table would look like this based on three potential scenarios.

AMD's 25x20 Goal: Future?
R15 nT
3DMark 11 P Variable C Variable E Performance
Same Power 2000 18000 8.51 0.34 25.04x
Half Power 1000 8000 4.02 0.16 25.14x
Low Power 800 4400 2.75 0.11 25.01x
Raven Ridge 719 4315 2.56 0.44 5.86x
Bristol Ridge 279 3234 1.36 0.34 3.97x
Carrizo 277 2709 1.23 0.35 3.51x
Kaveri 232 2142 1.00 1.00 1.00x

In the same power scenario (0.34E, like Bristol Ridge), AMD would have to severely increase both CPU performance by 3x and GPU performance by over 4x. An obvious way to go in that direction would be to double everything, although that is not always an easy task when it requires keeping power the same, even over several generations. A crystal ball will predict 8-core laptops, though it will be interesting to see the power, the frequencies, and the process node.

For a half-power scenario (0.16E), we took the fact that AMD is likely to increase its IPC over the next few generations by 5-15% each year. By 2020, assuming the same core count as today, this would give a Cinebench score of about 1000. In order to reach the 25x performance efficiency metric with that increase in CPU performance, the GPU would have to almost double in performance. One of the outcomes of moving to 7nm could be that AMD keeps the quad-core design but instead increases the number of compute units in the integrated GPU. Doubling the compute units, halving the power consumption, and increasing IPC by 30% is a tall order in three years, even with a node change and new architectures.

Ryan’s preferred option is the low power scenario. If AMD created a 4.5W-like processor which overall reduced the variable ‘E’ by ~75%, along with the general system improvements like LPDDR, but kept about the same performance as the 15W chips of today, then AMD could hit the 25x metric fairly comfortably. This might be considered an easier task than the others, and it will depend on how AMD is able to manage the power with such a low ceiling.

This is where I put in a poll to see what people think of where AMD will sit come 2020:

I have set the poll to last for 7 days. The results should speak for themselves.

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  • jospoortvliet - Saturday, October 28, 2017 - link

    Thing is - a typical laptop is idle >95% of the time ;-)

    I don't know exactly what the amount of RAM activity is when you are, say, typing a comment in browser but I'd be willing to bet it isn't so much that LPDDR3 uses more power than DDR4.
  • iwod - Thursday, October 26, 2017 - link

    The TSMC Roadmap: ( I remember posting this Anandtech Forum and people were calling me crazy....... )
    2018 - 7nm
    2019 - 7nm +
    2020 - 5nm

    GF runs a similar schedule. So we may see 5nm from GF in 2020 as well. ( Yes this 5nm is different from Intel's 5nm )

    That is a jump from 14nm > 12nm > 7nm > 7nm+ / EUV > 5nm

    Roughly 4x the density. Along with some other improvement that should scale well on the GPU performance side.

    If we just simply it to have 5x *Multithread* Cinebench and Graphics performance within the same power budget in 5 years time. This doesn't look too difficult, they have chosen a benchmark for performance that scales very nicely with more transistor.
  • nevcairiel - Friday, October 27, 2017 - link

    Even if the foundry plans for 5nm in 2020, you won't have shipping products yet.
  • DanNeely - Thursday, October 26, 2017 - link

    "That’s a steep hill to climb, and it is clear that the scale of the graph above seems to be wrong, with Ryzen Mobile being half-way up the graph, rather than around 20% up the graph."


    Of all the editors here, I'd've expected you to be able to identify a log scale plot even with an unlabeled axis. Something where exponential growth would be expected showing as a fixed slope should have been a dead giveaway.
  • Ian Cutress - Thursday, October 26, 2017 - link

    Sorry to disappoint. I was finishing it up at 6am...
  • vladx - Thursday, October 26, 2017 - link

    The "Half Power" scenario seems most likely looking at future improvements in fab node.
  • ikjadoon - Thursday, October 26, 2017 - link

    Minor typo:

    To calculate C, we have to go to the Energy Star documents and pull out this long equation:

    Should read "To calculate E...", no?
  • ikjadoon - Thursday, October 26, 2017 - link

    And that's why everyone says, "Label your axes."

    I think logarithmic is not a fair representation, given that the first 5x improvement is much easier than the 2nd "5x".
  • bcronce - Friday, October 27, 2017 - link

    *My opinion* is that log scale is fair because most things related to silicon scale exponentially. Some thing event scale a mixture of exponential and quadratic with something like O(2^N*M^2). Of course (2^N) wins in the long run, but you see the scaling going faster than (2^N) on its own.
  • Ramman.K - Thursday, October 26, 2017 - link

    Was there any information about upcoming mobile CPUs for workhorse laptops (think XPS15 cores/performance) ???

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