When AMD started using TSMC’s 7nm process for the Zen 2 processor family that launched in November 2019, one of the overriding messages of that launch was that it was important to be on the leading edge of process node technology to be competitive. That move to TSMC N7 was aided by the small chiplets used in the desktop processors at the time, ensuring a higher yield and better binning curves for desktop and enterprise processors. However, between now and then, we’ve seen other companies take advantage of TSMC’s 5nm, 4nm, and talk about TSMC’s 3nm process coming to market over the next 12-24 months. During our roundtable discussion with CEO Dr. Lisa Su, I asked if the need to stay on the leading edge still held true.

To put this into perspective, AMD announced late in 2021 that it would be using TSMC’s 5nm process for its Zen 4 chiplets in enterprise CPUs in the second half of 2022. Then in early 2022, the company reiterated the use of Zen 4 chiplets, but this time in desktop processors again by the end of 2022. This is a significant delay between the first use of TSMC 5nm by the smartphone vendors, which reached mass production in Q3 2020, with Apple and Huawei being the first to take advantage. Even today, if we go beyond 5nm, Mediatek has already announced that its upcoming Dimensity 9000 smartphone chip is on TSMC 4nm and will come to market earlier this year. TSMC’s 3nm process is expected to ramp production at the end of 2022, for a consumer launch in early 2023. By those metrics, AMD is behind a process node or two by the time Zen 4 chiplets come to market later this year.

I asked Dr. Su in our roundtable about whether the need to be on the leading edge process is critical to be competitive for them. Having innovated around chiplets, I asked whether being the lead partner with foundry partners and packaging partners (known as OSATs) is of major importance, especially when the lead competition seem ready to throw money at TSMC to take that volume. How would AMD be able to aggressively assert a market-leading position in light of the complexity of manufacturing and the financial power of the competition?

Dr. Su stated that AMD is continuing to innovate in all areas. For AMD it seems, leading the chiplet technology has helped to bring the package together. She went on to say that AMD has had strong delivery of 7nm, is introducing 6nm, followed by Zen 4 and 5nm, talking about 2D chiplets and 3D chiplets – AMD has all these things in the tool chest and are using the right technology for the right application. Dr Su reinforced that technology roadmaps are all about making the right choices and the right junctures, and explicitly stated that our 5nm technology is highly optimized for high-performance computing – it’s not necessarily the same as some other 5nm technologies out there.

While not explicitly stating that the need to be leading edge is no longer critical, this messaging follows the enhanced narrative from AMD that in the era of chiplets, it’s how they’re combined and packaged that is becoming important, arguably more important than exactly what process node is being used. We’ve seen this messaging before from AMD’s main competitor Intel, where back in 2017 the company stated that it will heavily rely on optimized chiplets for each use case – this was crystallized further in 2020 suggesting 24-36 chiplets on a single consumer desktop processor for purpose-built client designs. That being said, it has been constantly rumored that Intel will be a big customer of TSMC 3nm in the following years, so it will be interesting to see where AMD can take advantage of several years of chiplet expertise and packaging tools by comparison.

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  • Matthias B V - Tuesday, January 11, 2022 - link

    It won't be N4X as this arrives way later. There is two reasonable options in my opinion AMD will use: Regular improved N5P [with slightly adjusted libraries] or N5HPC [which is expected H2/2022].

    TSMC N4X as version to N4 is 2023/24 and beyond. However I guess as TSMC has N7HPC and N5HPC I would asume N4X is just a similar process with different naming sheme. Also N4X seems quite close to N3 and N4P to what is possible so I am not sure if we see a lot N4X...
    Reply
  • repoman27 - Tuesday, January 11, 2022 - link

    Yeah, N5HPC lines up pretty darn well, and with volume production slated for Q2'22. Of course TSMC also uses HPC to refer to one of the libraries they typically offer with each node, along with HD (High Density) and, beginning with N3, HC (High Current). AMD may be employing some additional DTCO here as well.

    Here's a link with a little more info on the HPC flavors: https://community.cadence.com/cadence_blogs_8/b/br...
    Reply
  • repoman27 - Monday, January 10, 2022 - link

    This paragraph is preposterous: "Even today, if we go beyond 5nm, Mediatek has already announced that its upcoming Dimensity 9000 smartphone chip is on TSMC 4nm and will come to market earlier this year. TSMC’s 3nm process is expected to ramp production at the end of 2022, for a consumer launch in early 2023. By those metrics, AMD is behind a process node or two by the time Zen 4 chiplets come to market later this year."

    Let me get this straight, no products using TSMC N4 have actually shipped yet, and N3 will not ship until next year, but AMD will be behind by a process node or two when they ship N5 products later this year?!?

    If AMD intended to ship a product in 2022, N3 was not an appropriate choice, because it would not have been available in time. That's why Apple will be using N4 for the A16. N4 is just an extension of N5, using the same design rules with a 6% optical shrink. N5P is also an extension of N5 and actually offers higher performance at ISO power than N4 despite not getting the optical shrink or perhaps using quite as many EUV layers. It's also what Apple uses for the A15, which was released just over a quarter ago. Your metrics are way, way off if you think that N5P in 2022 constitutes being behind by 1 to 2 process nodes.
    Reply
  • ikjadoon - Monday, January 10, 2022 - link

    I mean...

    AMD Zen3 (on N7): Q4 2020
    TSMC N5: Q4 2020

    AMD Zen4 (on N5-class): Q4 2022
    TSNC N3: Q1 2023

    Your use of years is a little misleading. AMD is genuinely barely missing the latest nodes' high-volume phase either by weeks or a quarter at most. Likewise, AMD CPUs stay a while on the market, so just missing the latest node does put them at a node disadvantage of at least one full node. It is more cost effective for AMD (not that they're still passing along those savings...) to not align their releases with the latest nodes.

    If Apple could pivot to N4, so could've AMD. Goodness knows Apple has to deal with an order of magnitude higher volume & far stricter deadlines.
    Reply
  • repoman27 - Monday, January 10, 2022 - link

    No it's not misleading at all. Because AMD isn't planning a Dec 31, 2022 release for Zen 4. TSMC N3 will barely be emerging from risk production when AMD plans on shipping Ryzen 7000. AMD will also be shipping a fully validated server platform, one that is already sampling to customers, before the first client N3 products hit the market. The only realistic take here is that when AMD ships Zen 4, it will in fact be manufactured on the highest performance and most advanced process available at that time. Waiting a year for N3 or two years for N2 was not a viable an option.

    And once again, AMD chose N5P because it is *higher perfomance* than N4. Apple cares more about area and power rather than outright performance because they're making smartphone chips.
    Reply
  • Silver5urfer - Monday, January 10, 2022 - link

    Makes sense.

    Also AMD doesn't need to be on 3nm because Intel is far behind at 10nm / 7nm level. Plus high power CPUs need to be on the most optimized for high performance processors than those BGA use and throw smartphone processors.

    Apple pays a ton so they get that top first batch from TSMC.
    Reply
  • repoman27 - Monday, January 10, 2022 - link

    Here are the logic densities of everything on the roadmap from TSMC or Intel for the next three years:

    TSMC N5/N5P = 171.3 MTr/mm² (1.0x)
    TSMC N4/N4P/N4X = 182.23 MTr/mm² (1.06x)
    Intel 4/3 <= 237.18 MTr/mm² (1.4x)
    TSMC N3/N3E = 291.21 MTr/mm² (1.7x)

    If you take 2.0x as being the traditional density scaling factor for a new process node, AMD will never be one full node behind, let alone two nodes. Furthermore, they will be on a more advanced process than Intel in both the desktop and server spaces for close to a year if not longer. TSMC N5/N5P also happens to be 1.7x the density of Intel 7, which is what Intel is using for Alder Lake, Raptor Lake, Sapphire Rapids, and Emerald Rapids.

    Sorry to keep harping on about this, but my mind boggles at the sophistic bullshit that Ian presented in this post.
    Reply
  • cheshirster - Tuesday, January 11, 2022 - link

    Good points you have. Reply
  • Wilco1 - Tuesday, January 11, 2022 - link

    We haven't seen 2x node scaling for a long time (last time Intel tried it, they failed badly). A full node scaling is ~1.6-1.8x for TSMC. You're right that saying AMD is 2 nodes behind is wrong given that N4/N4P are not all that different from N5P.

    However consider this: in 12-15 months there will be various 3nm products. If AMD sticks to a 24 month schedule, they might use N3E in mid/late 2024. That means they will be a full node behind for about 18 months.

    None of this matters for desktops since the main competition is Intel, but it does for laptops and servers where there is increasing competition from Ampere, Apple, Qualcomm, Alibaba, AWS Graviton etc.
    Reply
  • repoman27 - Tuesday, January 11, 2022 - link

    Area scaling from TSMC N7 to N4 (the compact version of N5) is 2x. We're still getting full nodes, just not in one bite. Intel switched to hyper-scaling as they adopted multi-patterning, and you're right, it didn't work. However, they were attempting 2.45x scaling with 14nm and 2.7x with 10nm, which is crazy aggressive.

    Zen4+ on N4X would require minimal redesign and could ship H1'24. N4X should offer equivalent performance to base N3, albeit at lower density.

    AMD will only be behind once products they actually compete against are manufactured on a more advanced node and become available in the market. For Intel, AMD's primary competitor, the only thing on the horizon is Meteor Lake in H1'23. That's a Foveros design using Intel 7, Intel 4, and possibly TSMC N4 and N3, and it looks like the ULV (U9/U15) chips will be the first out the gate. Apple could potentially release an M2 on N4 in Q4'22, but they still haven't released their HEDT / workstation class chips on N5 yet. Q4'23 is the earliest they would have any M series chips on N3, and they certainly wouldn't be starting with the higher performance chips. Off the top of my head, I can't speak to the ARM server vendors' plans.
    Reply

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