Marvell Announces NVMe Controller for DRAM-Less PCIe 3.0 x2 SSDs
by Anton Shilov on August 17, 2016 7:30 PM EST
Marvell has announced its new controller for affordable and miniature SSDs, the 88NV1160. The chip can be used to build small form-factor SSDs in M.2 as well as BGA packages. The 88NV1160 supports all modern and upcoming types of NAND flash, LDPC error correction, NVMe protocol and other advantages of modern SSD controllers, but it does not require external DRAM buffers so to reduce BOM costs of upcoming SSDs.
The Marvell 88NV1160 is a quad-channel controller that supports PCIe 3.0 x2 interface, NVMe 1.3 protocol (in addition to AHCI) as well as various types of NAND flash memory, including 15 nm TLC, 3D TLC as well as 3D QLC with ONFI 3.0 interface with up to 400 MT/s transfer rates. The 88NV1160 controller is powered by dual-core ARM Cortex-R5 CPUs along with embedded SRAM with hardware accelerators to optimize IOPS performance. The chip supports Marvell’s third-generation LDPC error correction technology (which the company calls NANDEdge ECC) in a bid to enable high endurance of drives featuring ultra-thin TLC or 3D QLC memory.
| Specifications of Marvell 88NV1160 at Glance | |
| Compute Cores | Two ARM Cortex-R5 |
| Host Interface | PCIe 3.0 x2 |
| Protocol of Host Interface | AHCI, NVMe 1.3 |
| Supported NAND Flash Types | 15 nm TLC 3D TLC 3D QLC |
| Supported NAND Flash Interfaces | Toggle 2.0 and ONFi 3.0, up to 400 MT/s |
| Page Sizes | Unknown |
| Number of NAND Channels | 4 channels with 4 CE per channel (16 targets in total) |
| ECC Technology | LDPC (third-generation LDPC ECC by Marvell) |
| Maximum SSD Capacity | 1024 GB (when using 3D QLC ICs with 512 Gb capacity) |
| Maximum Sequential Read Speed | 1600 MB/s |
| Maximum Sequential Write Speed | Unknown, depends on exact type of memory |
| Power Management | Low power management (L1.2) design |
| Package | 9 × 10 mm TFBGA package |
| Voltages | 3.3V/1.8V/1.2V power supply (according to M.2 specs) |
The 88NV1160 controller is specifically tailored for upcoming affordable SSDs, which is why it does not officially support SLC and 2D MLC NAND. Maximum capacity of a 3D QLC-based SSD featuring the 88NV1160 controller is expected to be around 1 TB, which should be enough for entry-level SSDs (as well as solid-state storage solutions for premium tablets, ultrabooks and other types of computing devices). As for performance, Marvell mentioned 1600 MB/s maximum read speed for such SSDs.
The new chip from Marvell is made using 28 nm process technology and is shipped in 9 × 10 mm TFBGA package, which can be used to build SSDs in BGA (M.2-1620 and smaller) packages as well as drives in M.2-2230/2242 form-factors. The 88NV1160 controller uses 3.3V/1.8V/1.2V power supply, in accordance with the M.2 standards.
The 88NV1160 is not the first controller from Marvell that does not require any external DRAM buffers. The company also offers low-cost 88NV1120 with SATA interface as well as 88NV1140 for PCIe 3.0 x1 SSDs. All of the aforementioned controllers are based on two ARM Cortex-R5 cores, feature Marvell’s third-gen LDPC implementation and support modern types of NAND flash memory (15nm 2D TLC and 3D TLC/QLC). However, the new 88NV1160 is the newest DRAM-less controller from the company, which is designed for rather advanced SSDs with up to 1600 MB/s read speed. Still, the 88NV1160 is clearly a solution for affordable drives because unlike the high-end 88SS1093 (or its less advanced brother, the 88SS1094) it does not support 2D MLC and SLC NAND flash and cannot take advantage of eight NAND channels (which is why it does not need PCIe 3.0 x4).
| Comparison of Modern SSD Controllers from Marvell | ||||||
| 88NV1120 | 88NV1140 | 88NV1160 | 88SS1093 | |||
| Compute Cores | Two ARM Cortex-R5 | Three cores | ||||
| Host Interface | SATA | PCIe 3.0 x1 | PCIe 3.0 x2 | PCIe 3.0 x4 | ||
| Protocol of Host Interface | AHCI | AHCI, NVMe 1.3 | NVMe 1.1 | |||
| Supported NAND Flash Types | 15 nm TLC 3D TLC 3D QLC |
15 nm SLC/MLC/TLC 3D NAND |
||||
| Number of NAND Channels | 2 channels 4 CE per channel (8 targets in total) |
4 channels 4 CE per channel (16 targets in total) |
8 channels 4 CE per channel (32 targets in total) |
|||
| ECC Technology | Marvell's third-gen LDPC-based ECC technology | |||||
| Host Memory Buffer | No | Yes | Yes | - | ||
| Package | 8 × 8 mm TFBGA |
9 × 10 mm TFBGA |
BGA | |||
| Compatibility | M.2/BGA SSDs | M.2/2.5" SSDs | ||||
The developer did not reveal when it expects the first SSDs based on the 88NV1160 controller to hit the market, but it indicated that the chip is available for sampling globally. In addition, the company indicated that it offers turnkey firmware to its customers so to enable faster time to market.
Source: Marvell
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extide - Thursday, August 18, 2016 - link
You're mad there are ARM cores on there instead of fixed function hardware? You know that pretty much all SSD controllers use some form of general purpose CPU, most of them Cortex R series. In fact most hard drives use Cortex R series cores as well.fanofanand - Tuesday, August 23, 2016 - link
Where do you see him being "mad"?mindless1 - Sunday, September 4, 2016 - link
Remember these are not enterprise solutions. Take the typical PC, with an owner that has $100 to spend. That will get a 240GB MLC SSD, but it will get a 480GB TLC. The extra 240GB is a whole lot of room for wear leveling, and just how many years is the owner going to keep using same PC before upgrading to SATA8 or whatever and a much larger SSD at that point in time?Remember that the most writes an average PC users does, is merely their browser caching what they surf, or the OS itself deciding what it wants to do. Many browsers can have their disk cache turned off, or with DRAM so cheap, disable pagefile too or divert to a ramdrive. Essentially most of the problems with lower write cycles are just badly written applications and OS that didn't keep up with hardware tech advances. It was just plain stupid all along that Windows incessantly writes to HDD, remember back in the day of win95 when you could be typing up an Office doc and the lone HDD would actually time out and sleep after 15 minutes if your autosave interval was longer than that, and this with only 32MB main memory. It's almost shameful how much of a waste modern hardware is.
jjj - Thursday, August 18, 2016 - link
Sounds great.Very few need even more perf so a budget solution that is a lot faster than SATA is exactly what was needed.Hopefully random perf is decent too.msroadkill612 - Thursday, September 21, 2017 - link
Hesitantly waxing philosophical if I may, the whole storage thing seems primitive vs best practice in the hard copy paradigm.Methods like; raid0, raid 5, full backups, a single primary source for a file, all files in same similar storage reqardless of usage or urgency - all seem to have little connection with how a library/office/government... would have organised and secured their records of yore.
We may install an important app on our premium storage, but many of the files may be rarely used or non urgent, but we are too short of unaffordable premium space for apps with files that could profit from relocating to better media. Any kind of manual speed tuning becomes exhausting and fraught, fast.
As a poster here said, all types of storage have some use, somewhere in the server world. It exist there, but it seems a killer mainstream app too - to interpose an overall file controller, which intelligently manages a hierarchical pool of storage resources.
all we want is that we get; prompt, security, ~fireproof, work resumed ~fast after a lesser fail, no zillions of duplicates on premium storage ~as now, files on optimal media given usage patterns,....
It ties in also with the very modern problem of minimising cloud backup storage charges. Duplicates waste $.
To illustrate, a cheap ~8GB pc; raid 0 pair of 128GB nvme, 256g nvme, sata hdd, sata hdd raid, esata for full archives, would offer the ~gamut of media in even stages of strengths and weaknesses.
Let the computer juggle them into something much greater than the sum of the parts.
Vega's HBCC seems a step in this direction - managing a cache pool, which includes storage and nvme.